Abstract
The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.
| Original language | English |
|---|---|
| Pages (from-to) | 1126-1141 |
| Number of pages | 16 |
| Journal | IEEE Transactions on Parallel and Distributed Systems |
| Volume | 20 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2009 |
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Keywords
- Interconnection networks
- Network topology
- On-chip networks
- Routing algorithm
- Tree
ASJC Scopus subject areas
- Hardware and Architecture
- Signal Processing
- Computational Theory and Mathematics
Cite this
Fat H-Tree : A cost-efficient tree-based on-chip network. / Matsutani, Hiroki; Koibuchi, Michihiro; Yamada, Yutaka; Hsu, D. Frank; Amano, Hideharu.
In: IEEE Transactions on Parallel and Distributed Systems, Vol. 20, No. 8, 2009, p. 1126-1141.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Fat H-Tree
T2 - A cost-efficient tree-based on-chip network
AU - Matsutani, Hiroki
AU - Koibuchi, Michihiro
AU - Yamada, Yutaka
AU - Hsu, D. Frank
AU - Amano, Hideharu
PY - 2009
Y1 - 2009
N2 - The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.
AB - The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.
KW - Interconnection networks
KW - Network topology
KW - On-chip networks
KW - Routing algorithm
KW - Tree
UR - http://www.scopus.com/inward/record.url?scp=67650667517&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67650667517&partnerID=8YFLogxK
U2 - 10.1109/TPDS.2008.233
DO - 10.1109/TPDS.2008.233
M3 - Article
AN - SCOPUS:67650667517
VL - 20
SP - 1126
EP - 1141
JO - IEEE Transactions on Parallel and Distributed Systems
JF - IEEE Transactions on Parallel and Distributed Systems
SN - 1045-9219
IS - 8
ER -