Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Based on the power consumption analysis of a real Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the Processing Element (PE) array as possible. Fine Grain Partial Reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average.

Original languageEnglish
Title of host publicationFPL 09
Subtitle of host publication19th International Conference on Field Programmable Logic and Applications
Pages530-533
Number of pages4
DOIs
Publication statusPublished - 2009 Nov 25
EventFPL 09: 19th International Conference on Field Programmable Logic and Applications - Prague, Czech Republic
Duration: 2009 Aug 312009 Sep 2

Publication series

NameFPL 09: 19th International Conference on Field Programmable Logic and Applications

Other

OtherFPL 09: 19th International Conference on Field Programmable Logic and Applications
CountryCzech Republic
CityPrague
Period09/8/3109/9/2

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

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  • Cite this

    Sano, T., Saito, Y., Kato, M., & Amano, H. (2009). Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors. In FPL 09: 19th International Conference on Field Programmable Logic and Applications (pp. 530-533). [5272435] (FPL 09: 19th International Conference on Field Programmable Logic and Applications). https://doi.org/10.1109/FPL.2009.5272435