Flexible hardware design methodology for high-performance atm switching system using real-time emulation technique

Tsuneo Matsumura, Naoaki Yamanaka, Ryoichi Yamaguchi, Keiji Ishikawa

Research output: Contribution to journalArticle

Abstract

In the first stage of ATM switching system development, the specifications are sometimes changed in order to match revisions in ITU standards. Fatal problems due to specification changes and unexpected bugs force ASIC redesign and subsequent debugging is seriously restricted. These situations demand the introduction of new hardware design methodologies. This paper proposes a flexible hardware design methodology, based on a novel real-time emulation technique, suitable for large-scale high-speed communication switching systems. The emulation technique offers desirable system performance without Application Specific Integrated Circuit (ASIC) fabrication by using commercial Field Programmable Gate Arrays (FPGAs) along with many simply-structured high-speed interconnect switch devices for multiple FPGA connection. This technique suits line interface units (LUs) that have ASICs operating at about 20 MHz; each LU employs an LU board and emulation boards, both of which have hierarchical structures with sub-boards. The emulation boards are indispensable for realizing prototype systems rapidly and dealing with specification changes. Different types of LUs can be realized by mounting different sub-boards to the common LU board. Each emulation board is attached to the LU board by the same connector used for LU sub-board mounting. Therefore, the proposed structure has the advantage of utilizing a common LU board for system emulation as well as permitting the development of practical systems. To suppress undesirable multiple FPGA partitioning, we propose the emulation board architecture that has two types of sub-boards, each of which carries a different type of FPGA. We produced some portions of the proposed LU and tested the nearly 20 MHz real-time emulation of a complicated ASIC designed to realize ATM cell header conversion functions. The results of multiple FPGA partitioning on the emulation board suggest that the proposed design methodology will yield economic systems that can be freely modified to overcome hardware bugs and comply with future ITU standards.

Original languageEnglish
Pages (from-to)466-471
Number of pages6
JournalIEICE Transactions on Communications
VolumeE81-B
Issue number2
Publication statusPublished - 1998
Externally publishedYes

Fingerprint

Switching systems
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware
Automatic teller machines
Specifications
Mountings
Switches
Fabrication
Economics
Communication

Keywords

  • Atm switching system, lu
  • Emulation
  • FPGA
  • Interconnect device

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

Cite this

Flexible hardware design methodology for high-performance atm switching system using real-time emulation technique. / Matsumura, Tsuneo; Yamanaka, Naoaki; Yamaguchi, Ryoichi; Ishikawa, Keiji.

In: IEICE Transactions on Communications, Vol. E81-B, No. 2, 1998, p. 466-471.

Research output: Contribution to journalArticle

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