Folded fat H-Tree

An interconnection topology for dynamically reconfigurable processor array

Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing. For on-chip implementation, folding layout is also proposed. Evaluation results show that Fat H-Tree reduces the distance of H-Tree from 13% to 55%, and stretches the throughput almost three times.

Original languageEnglish
Pages (from-to)301-311
Number of pages11
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3207
Publication statusPublished - 2004

Fingerprint

Parallel processing systems
Oils and fats
Interconnection
Fats
Topology
Chip
Trees (mathematics)
Stream Processing
Stretch
Folding
Throughput
Network Topology
Layout
Torus
Processing
Evaluation

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

Folded fat H-Tree : An interconnection topology for dynamically reconfigurable processor array. / Yamada, Yutaka; Amano, Hideharu; Koibuchi, Michihiro; Jouraku, Akiya; Anjo, Kenichiro; Nishimura, Katsunobu.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3207, 2004, p. 301-311.

Research output: Contribution to journalArticle

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