TY - JOUR
T1 - GenMap
T2 - A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures
AU - Kojima, Takuya
AU - Doan, Nguyen Anh Vu
AU - Amano, Hideharu
N1 - Funding Information:
Manuscript received March 6, 2020; revised May 21, 2020 and June 14, 2020; accepted July 10, 2020. Date of publication July 27, 2020; date of current version October 23, 2020. This work was supported in part by JSPS KAKENHI Grant 18H03215 and Grant 19J21493, in part by the VLSI Design and Education Center (VDEC), The University of Tokyo, in collaboration with Synopsys, Inc., and Cadence Design Systems, Inc., and in part by JST CREST under Grant JPMJCR19K1, Japan. (Corresponding author: Takuya Kojima.) Takuya Kojima and Hideharu Amano are with the Department of Information and Computer Science, Keio University, Tokyo 223-8522, Japan (e-mail: tkojima@am.ics.keio.ac.jp; hunga@am.ics.keio.ac.jp).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2020/11
Y1 - 2020/11
N2 - Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%-46.8% of energy consumption is reduced, and up to 2\times speedup is archived for several architectures when compared with other two approaches.
AB - Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%-46.8% of energy consumption is reduced, and up to 2\times speedup is archived for several architectures when compared with other two approaches.
KW - Body bias control
KW - coarse-grained reconfigurable architecture (CGRA)
KW - genetic algorithm
KW - mapping optimization
KW - multiobjective optimization
KW - variable pipeline
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U2 - 10.1109/TVLSI.2020.3009225
DO - 10.1109/TVLSI.2020.3009225
M3 - Article
AN - SCOPUS:85094872678
VL - 28
SP - 2383
EP - 2396
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 11
M1 - 9149647
ER -