Geyser-2

The second prototype CPU with fine-grained run-time power gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, Hideharu Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)
Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages87-88
Number of pages2
DOIs
Publication statusPublished - 2011
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: 2011 Jan 252011 Jan 28

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period11/1/2511/1/28

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Program processors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., ... Kondo, M. (2011). Geyser-2: The second prototype CPU with fine-grained run-time power gating. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 87-88). [5722310] https://doi.org/10.1109/ASPDAC.2011.5722310

Geyser-2 : The second prototype CPU with fine-grained run-time power gating. / Zhao, L.; Ikebuchi, D.; Saito, Y.; Kamata, M.; Seki, N.; Kojima, Y.; Amano, Hideharu; Koyama, S.; Hashida, T.; Umahashi, Y.; Masuda, D.; Usami, K.; Kimura, K.; Namiki, M.; Takeda, S.; Nakamura, H.; Kondo, M.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2011. p. 87-88 5722310.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhao, L, Ikebuchi, D, Saito, Y, Kamata, M, Seki, N, Kojima, Y, Amano, H, Koyama, S, Hashida, T, Umahashi, Y, Masuda, D, Usami, K, Kimura, K, Namiki, M, Takeda, S, Nakamura, H & Kondo, M 2011, Geyser-2: The second prototype CPU with fine-grained run-time power gating. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 5722310, pp. 87-88, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, 11/1/25. https://doi.org/10.1109/ASPDAC.2011.5722310
Zhao L, Ikebuchi D, Saito Y, Kamata M, Seki N, Kojima Y et al. Geyser-2: The second prototype CPU with fine-grained run-time power gating. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2011. p. 87-88. 5722310 https://doi.org/10.1109/ASPDAC.2011.5722310
Zhao, L. ; Ikebuchi, D. ; Saito, Y. ; Kamata, M. ; Seki, N. ; Kojima, Y. ; Amano, Hideharu ; Koyama, S. ; Hashida, T. ; Umahashi, Y. ; Masuda, D. ; Usami, K. ; Kimura, K. ; Namiki, M. ; Takeda, S. ; Nakamura, H. ; Kondo, M. / Geyser-2 : The second prototype CPU with fine-grained run-time power gating. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2011. pp. 87-88
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