Geyser-2: The second prototype CPU with fine-grained run-time power gating

L. Zhao; D. Ikebuchi; Y. Saito; M. Kamata; N. Seki; Y. Kojima; H. Amano; S. Koyama; T. Hashida; Y. Umahashi; D. Masuda; K. Usami; K. Kimura; M. Namiki; S. Takeda; H. Nakamura; M. Kondo

doi:10.1109/ASPDAC.2011.5722310

Geyser-2: The second prototype CPU with fine-grained run-time power gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Original language	English
Title of host publication	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages	87-88
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2011.5722310
Publication status	Published - 2011 Mar 28
Event	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan Duration: 2011 Jan 25 → 2011 Jan 28

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Country/Territory	Japan
City	Yokohama
Period	11/1/25 → 11/1/28

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2011.5722310

Cite this

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H., & Kondo, M. (2011). Geyser-2: The second prototype CPU with fine-grained run-time power gating. In 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 (pp. 87-88). [5722310] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722310

Geyser-2: The second prototype CPU with fine-grained run-time power gating. / Zhao, L.; Ikebuchi, D.; Saito, Y. et al.
2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. 2011. p. 87-88 5722310 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhao, L, Ikebuchi, D, Saito, Y, Kamata, M, Seki, N, Kojima, Y, Amano, H, Koyama, S, Hashida, T, Umahashi, Y, Masuda, D, Usami, K, Kimura, K, Namiki, M, Takeda, S, Nakamura, H & Kondo, M 2011, Geyser-2: The second prototype CPU with fine-grained run-time power gating. in 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011., 5722310, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 87-88, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, 11/1/25. https://doi.org/10.1109/ASPDAC.2011.5722310

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Geyser-2: The second prototype CPU with fine-grained run-time power gating

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ASJC Scopus subject areas

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