Glitch-aware variable pipeline optimization for CGRAs

Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Although some coarse grained reconfigurable arrays (CGRAs) have a function to unify multiple processing elements (PEs) to enhance the energy efficiency, it sometimes causes propagation of glitches widely resulting in the power increases. We propose a dynamic power model considering glitches and an optimization technique using it for CGRAs. The model aims to estimate the energy consumption from the switching counts of a PE array approximately. The model and optimization were applied to a real chip of the low power CGRA called the VPCMA (Variable Pipeline Cool Mega Array). Compared with the energy estimation with a post-layout simulation, the model could estimate it with more than 10000 times faster with smaller error from the results of the real chip measurement. The optimized pipeline structure using the proposed method achived better energy consumption compared to fixed pitch pipeline structures in most cases.

Original languageEnglish
Title of host publication2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-6
Number of pages6
Volume2018-January
ISBN (Electronic)9781538637975
DOIs
Publication statusPublished - 2018 Feb 2
Event2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 - Cancun, Mexico
Duration: 2017 Dec 42017 Dec 6

Other

Other2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
CountryMexico
CityCancun
Period17/12/417/12/6

Fingerprint

Pipelines
Energy utilization
Processing
Energy efficiency

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture

Cite this

Kojima, T., Ando, N., Okuhara, H., & Amano, H. (2018). Glitch-aware variable pipeline optimization for CGRAs. In 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 (Vol. 2018-January, pp. 1-6). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RECONFIG.2017.8279797

Glitch-aware variable pipeline optimization for CGRAs. / Kojima, Takuya; Ando, Naoki; Okuhara, Hayate; Amano, Hideharu.

2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-6.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kojima, T, Ando, N, Okuhara, H & Amano, H 2018, Glitch-aware variable pipeline optimization for CGRAs. in 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-6, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, 17/12/4. https://doi.org/10.1109/RECONFIG.2017.8279797
Kojima T, Ando N, Okuhara H, Amano H. Glitch-aware variable pipeline optimization for CGRAs. In 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-6 https://doi.org/10.1109/RECONFIG.2017.8279797
Kojima, Takuya ; Ando, Naoki ; Okuhara, Hayate ; Amano, Hideharu. / Glitch-aware variable pipeline optimization for CGRAs. 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-6
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