Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

Junichi Sawada, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

With the recent growth in the quantity and value of data, data holders have come to realize the importance of being able to utilize information that is otherwise abandoned or concealed. In this situation, they face the difficulty of publishing data without revealing private information. One of the methods used to protect private information when publishing data is privacy-preserving method based on constraints known as k-anonymity and l-diversity. In this paper, we propose a hardware architecture composed of Ternary Content Addressable Memory (TCAM) and a cache mechanism to efficiently reduce the time required for executing the methods. An evaluation proves that an implementation of the proposed architecture on a reconfigurable device performs approximately 10-50 times faster than a RAM-based architecture and up to 60% of the information loss can be eliminated by using the cache mechanism.

Original languageEnglish
Title of host publicationProceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Pages499-502
Number of pages4
DOIs
Publication statusPublished - 2012
Event22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway
Duration: 2012 Aug 292012 Aug 31

Other

Other22nd International Conference on Field Programmable Logic and Applications, FPL 2012
CountryNorway
CityOslo
Period12/8/2912/8/31

Fingerprint

Associative storage
Hardware
Data privacy
Random access storage

ASJC Scopus subject areas

  • Computer Science Applications

Cite this

Sawada, J., & Nishi, H. (2012). Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 499-502). [6339264] https://doi.org/10.1109/FPL.2012.6339264

Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. / Sawada, Junichi; Nishi, Hiroaki.

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 499-502 6339264.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sawada, J & Nishi, H 2012, Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012., 6339264, pp. 499-502, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 12/8/29. https://doi.org/10.1109/FPL.2012.6339264
Sawada J, Nishi H. Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 499-502. 6339264 https://doi.org/10.1109/FPL.2012.6339264
Sawada, Junichi ; Nishi, Hiroaki. / Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism. Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. pp. 499-502
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