Hardware accelerator for data anonymization using dynamic partial reconfiguration

Sota Sawaguchi, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Smart City is a promising infrastructure for our near future community systems. It is predicted that more and more sensor devices and computing resources will be deployed in access networks because of the Internet of Things (IoT). This movement can create a wide variety of new applications with different requirements of delay, privacy and locality. Smart community dictates less than 10ms communication as a control interval in order not to disturb the lifeline systems, such as power supply. As such, future devices should have the following attributes: low-power, low-latency, and flexibility for various applications. In this paper, we propose an energy-aware, low-latency, and flexible local device, such as gateway or coordinator, which integrates an SoC FPGA with dynamic partial reconfiguration (DPR) feature to grapple with data anonymization. The data anonymization is important to protect private information in smart community because domestic human activities can be, for example, estimated by exploiting electric power consumption data, which is known as nonintrusive load monitoring (NILM). However, anonymization operations usually require processing cost at the order of O(n2) where n denotes the number of data in a privacy processing window. In case of encapsulating privacy information in a local network, privacy preserving computation should be achieved in a local device. Hence, we have implemented four primitive operations using DPR for various anonymization purposes. The proposed system achieves 18-328 times better performance and 10-200 times lower power consumption in every primitive anonymization method than Raspberry Pi 2 Model B.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Smart Grid Communications, SmartGridComm 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages98-103
Number of pages6
ISBN (Electronic)9781509040759
DOIs
Publication statusPublished - 2016 Dec 8
Event7th IEEE International Conference on Smart Grid Communications, SmartGridComm 2016 - Sydney, Australia
Duration: 2016 Nov 62016 Nov 9

Other

Other7th IEEE International Conference on Smart Grid Communications, SmartGridComm 2016
CountryAustralia
CitySydney
Period16/11/616/11/9

Keywords

  • Anonymization
  • Dynamic partial reconfiguration
  • FPGA
  • Smart Community
  • Zynq

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Energy Engineering and Power Technology
  • Control and Optimization
  • Signal Processing

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  • Cite this

    Sawaguchi, S., & Nishi, H. (2016). Hardware accelerator for data anonymization using dynamic partial reconfiguration. In 2016 IEEE International Conference on Smart Grid Communications, SmartGridComm 2016 (pp. 98-103). [7778745] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SmartGridComm.2016.7778745