Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho; Kihara Taku; Arakawa Yutaka; Yamanaka Naoaki; Shiba Kosuke

doi:10.1109/ECOC.2008.4729415

Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Arakawa Yutaka, Yamanaka Naoaki, Shiba Kosuke

Department of Information and Computer Science

Research output: Contribution to conference › Paper › peer-review

Abstract

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

Original language	English
DOIs	https://doi.org/10.1109/ECOC.2008.4729415
Publication status	Published - 2008
Event	2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, Belgium Duration: 2008 Sept 21 → 2008 Sept 25

Other

Other	2008 34th European Conference on Optical Communication, ECOC 2008
Country/Territory	Belgium
City	Brussels
Period	08/9/21 → 08/9/25

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/ECOC.2008.4729415

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title = "Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks",

abstract = "A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.",

author = "Shimizu Sho and Kihara Taku and Arakawa Yutaka and Yamanaka Naoaki and Shiba Kosuke",

year = "2008",

doi = "10.1109/ECOC.2008.4729415",

language = "English",

note = "2008 34th European Conference on Optical Communication, ECOC 2008 ; Conference date: 21-09-2008 Through 25-09-2008",

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T1 - Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

AU - Sho, Shimizu

AU - Taku, Kihara

AU - Yutaka, Arakawa

AU - Naoaki, Yamanaka

AU - Kosuke, Shiba

PY - 2008

Y1 - 2008

N2 - A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

AB - A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

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U2 - 10.1109/ECOC.2008.4729415

DO - 10.1109/ECOC.2008.4729415

M3 - Paper

AN - SCOPUS:60449090927

T2 - 2008 34th European Conference on Optical Communication, ECOC 2008

Y2 - 21 September 2008 through 25 September 2008

ER -

Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Abstract

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ASJC Scopus subject areas

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