Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Arakawa Yutaka, Naoaki Yamanaka, Shiba Kosuke

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

Original languageEnglish
Title of host publicationEuropean Conference on Optical Communication, ECOC
DOIs
Publication statusPublished - 2008
Event2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, Belgium
Duration: 2008 Sep 212008 Sep 25

Other

Other2008 34th European Conference on Optical Communication, ECOC 2008
CountryBelgium
CityBrussels
Period08/9/2108/9/25

Fingerprint

Multilayers
Engines
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Sho, S., Taku, K., Yutaka, A., Yamanaka, N., & Kosuke, S. (2008). Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. In European Conference on Optical Communication, ECOC [4729415] https://doi.org/10.1109/ECOC.2008.4729415

Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. / Sho, Shimizu; Taku, Kihara; Yutaka, Arakawa; Yamanaka, Naoaki; Kosuke, Shiba.

European Conference on Optical Communication, ECOC. 2008. 4729415.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sho, S, Taku, K, Yutaka, A, Yamanaka, N & Kosuke, S 2008, Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. in European Conference on Optical Communication, ECOC., 4729415, 2008 34th European Conference on Optical Communication, ECOC 2008, Brussels, Belgium, 08/9/21. https://doi.org/10.1109/ECOC.2008.4729415
Sho S, Taku K, Yutaka A, Yamanaka N, Kosuke S. Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. In European Conference on Optical Communication, ECOC. 2008. 4729415 https://doi.org/10.1109/ECOC.2008.4729415
Sho, Shimizu ; Taku, Kihara ; Yutaka, Arakawa ; Yamanaka, Naoaki ; Kosuke, Shiba. / Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. European Conference on Optical Communication, ECOC. 2008.
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