Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Arakawa Yutaka, Yamanaka Naoaki, Shiba Kosuke

Research output: Contribution to conferencePaper

Abstract

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

Original languageEnglish
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, Belgium
Duration: 2008 Sep 212008 Sep 25

Other

Other2008 34th European Conference on Optical Communication, ECOC 2008
CountryBelgium
CityBrussels
Period08/9/2108/9/25

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Sho, S., Taku, K., Yutaka, A., Naoaki, Y., & Kosuke, S. (2008). Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks. Paper presented at 2008 34th European Conference on Optical Communication, ECOC 2008, Brussels, Belgium. https://doi.org/10.1109/ECOC.2008.4729415