Hardware/software co-design architecture for Blokus Duo solver

Naru Sugimoto, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.

Original languageEnglish
Title of host publicationProceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages358-361
Number of pages4
ISBN (Electronic)9781479962457
DOIs
Publication statusPublished - 2014
Event13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China
Duration: 2014 Dec 102014 Dec 12

Other

Other13th International Conference on Field-Programmable Technology, FPT 2014
CountryChina
CityShanghai
Period14/12/1014/12/12

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

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  • Cite this

    Sugimoto, N., & Amano, H. (2014). Hardware/software co-design architecture for Blokus Duo solver. In Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014 (pp. 358-361). [7082820] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPT.2014.7082820