Hardware/software co-design architecture for Blokus Duo solver

Naru Sugimoto; Hideharu Amano

doi:10.1109/FPT.2014.7082820

Hardware/software co-design architecture for Blokus Duo solver

Naru Sugimoto, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.

Original language	English
Title of host publication	Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	358-361
Number of pages	4
ISBN (Electronic)	9781479962457
DOIs	https://doi.org/10.1109/FPT.2014.7082820
Publication status	Published - 2014
Event	13th International Conference on Field-Programmable Technology, FPT 2014 - Shanghai, China Duration: 2014 Dec 10 → 2014 Dec 12

Other

Other	13th International Conference on Field-Programmable Technology, FPT 2014
Country/Territory	China
City	Shanghai
Period	14/12/10 → 14/12/12

ASJC Scopus subject areas

Computational Theory and Mathematics
Computer Science Applications

Access to Document

10.1109/FPT.2014.7082820

Cite this

Sugimoto, N & Amano, H 2014, Hardware/software co-design architecture for Blokus Duo solver. in Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014., 7082820, Institute of Electrical and Electronics Engineers Inc., pp. 358-361, 13th International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, 14/12/10. https://doi.org/10.1109/FPT.2014.7082820

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doi = "10.1109/FPT.2014.7082820",

language = "English",

pages = "358--361",

booktitle = "Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014",

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note = "13th International Conference on Field-Programmable Technology, FPT 2014 ; Conference date: 10-12-2014 Through 12-12-2014",

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AB - This paper presents a software and hardware design of an FPGA-based Blokus Duo solver. We used Embedded system called ZYNQ-7000 All Programmable SoC to implement the solver. By combining hardware with software, efficient acceleration is performed. Our system searches a game tree by using the miniMax algorithm with alpha-beta pruning. The implemented solver works at 75MHz with Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 on the Digilent ZedBoard. It can search states after three moves in most cases.

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BT - Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014

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ER -

Hardware/software co-design architecture for Blokus Duo solver

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