High-sensitivity 1-Gb/s CMOS receiver integrated with a III-V photodiode by wafer-bonding

Tatsushi Nakahara, Hiroyuki Tsuda, Kouta Tateno, Noboru Ishihara, Chikara Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A GaAs or InGaAs photodiode was attached to a 0.5-μm CMOS receiver circuit by a polyimide wafer-bonding technique. The circuit is simple and small, and has high sensitivity and a broad bandwidth due to the low parasitic capacitance on the photodiode. The receiver operates with a single 3.3-V supply voltage at either 0.85 or 1.55 μm and achieves -27.1-dBm sensitivity at 1 Gb/s.

Original languageEnglish
Title of host publicationLEOS Summer Topical Meeting
PublisherIEEE
Pages17-18
Number of pages2
Publication statusPublished - 2000
Externally publishedYes
Event2000 IEEE/LEOS Summer Topical Meeting - Aventura, FL, USA
Duration: 2000 Jul 242000 Jul 28

Other

Other2000 IEEE/LEOS Summer Topical Meeting
CityAventura, FL, USA
Period00/7/2400/7/28

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Atomic and Molecular Physics, and Optics

Cite this

Nakahara, T., Tsuda, H., Tateno, K., Ishihara, N., & Amano, C. (2000). High-sensitivity 1-Gb/s CMOS receiver integrated with a III-V photodiode by wafer-bonding. In LEOS Summer Topical Meeting (pp. 17-18). IEEE.