HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi, Y. Awano, M. Kosugi, T. Nagata, K. Kosemura, M. Ono, N. Kobayashi, H. Ishiwari, K. Odani, T. Mimura, M. Abe

Research output: Contribution to conferencePaper

22 Citations (Scopus)

Abstract

A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

Original languageEnglish
Pages177-180
Number of pages4
Publication statusPublished - 1987 Dec 1
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Notomi, S., Awano, Y., Kosugi, M., Nagata, T., Kosemura, K., Ono, M., Kobayashi, N., Ishiwari, H., Odani, K., Mimura, T., & Abe, M. (1987). HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.. 177-180.