HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi, Yuji Awano, M. Kosugi, T. Nagata, K. Kosemura, M. Ono, N. Kobayashi, H. Ishiwari, K. Odani, T. Mimura, M. Abe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

Original languageEnglish
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
PublisherIEEE
Pages177-180
Number of pages4
Publication statusPublished - 1987
Externally publishedYes

Fingerprint

Random access storage
High electron mobility transistors
Energy dissipation
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Notomi, S., Awano, Y., Kosugi, M., Nagata, T., Kosemura, K., Ono, M., ... Abe, M. (1987). HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 177-180). IEEE.

HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT. / Notomi, S.; Awano, Yuji; Kosugi, M.; Nagata, T.; Kosemura, K.; Ono, M.; Kobayashi, N.; Ishiwari, H.; Odani, K.; Mimura, T.; Abe, M.

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE, 1987. p. 177-180.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Notomi, S, Awano, Y, Kosugi, M, Nagata, T, Kosemura, K, Ono, M, Kobayashi, N, Ishiwari, H, Odani, K, Mimura, T & Abe, M 1987, HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT. in Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE, pp. 177-180.
Notomi S, Awano Y, Kosugi M, Nagata T, Kosemura K, Ono M et al. HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT. In Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE. 1987. p. 177-180
Notomi, S. ; Awano, Yuji ; Kosugi, M. ; Nagata, T. ; Kosemura, K. ; Ono, M. ; Kobayashi, N. ; Ishiwari, H. ; Odani, K. ; Mimura, T. ; Abe, M. / HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT. Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit). IEEE, 1987. pp. 177-180
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