HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi; Y. Awano; M. Kosugi; T. Nagata; K. Kosemura; M. Ono; N. Kobayashi; H. Ishiwari; K. Odani; T. Mimura; M. Abe

HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

S. Notomi, Y. Awano, M. Kosugi, T. Nagata, K. Kosemura, M. Ono, N. Kobayashi, H. Ishiwari, K. Odani, T. Mimura, M. Abe

Research output: Contribution to conference › Paper › peer-review

Abstract

A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

Original language	English
Pages	177-180
Number of pages	4
Publication status	Published - 1987 Dec 1
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.",

abstract = "A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.",

author = "S. Notomi and Y. Awano and M. Kosugi and T. Nagata and K. Kosemura and M. Ono and N. Kobayashi and H. Ishiwari and K. Odani and T. Mimura and M. Abe",

year = "1987",

month = dec,

day = "1",

language = "English",

pages = "177--180",

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TY - CONF

T1 - HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

AU - Notomi, S.

AU - Awano, Y.

AU - Kosugi, M.

AU - Nagata, T.

AU - Kosemura, K.

AU - Ono, M.

AU - Kobayashi, N.

AU - Ishiwari, H.

AU - Odani, K.

AU - Mimura, T.

AU - Abe, M.

PY - 1987/12/1

Y1 - 1987/12/1

N2 - A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

AB - A high speed 1K multiplied by 4-b static RAM has been designed and fabricated using 0. 5- mu m-gate HEMT (high-electron-mobility-transistor) technology. The address access time is 0. 5 ns and the chip power dissipation is 5. 7 W at room temperature. A summary of the RAM characteristics is presented.

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UR - http://www.scopus.com/inward/citedby.url?scp=0023541902&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0023541902

SP - 177

EP - 180

ER -

HIGH SPEED 1K multiplied by 4-BIT STATIC RAM USING 0. 5 mu M-GATE HEMT.

Abstract

ASJC Scopus subject areas

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