This letter describes the High-speed Statistical Retry switch (HSR switch) for high-speed ATM switching systems. The HSR switch uses a new matrix-shaped switching structure with buffers at input and output ports, and a simple retry algorithm. The input buffers are very small, and no complicated arbitration function is employed. A cell is repeatedly transmitted from each input buffer at 'm' times the input line speed until the input buffer receives an acknowledge signal from the intended output buffer. A maximum of one cell can be transmitted from each input buffer during the cell transmission time. The internal ratio (m) is decided according to the probability of cell conflict in the output line. Simulation results show that just a 10-cell buffer at each input port and a 50-cell buffer at each output port are required when m=4 to achieve a cell loss probability of better than 10-8, irrespective of the switch size. At each crosspoint, cells on the horizontal input line take precedence over those on the vertical input line. Only a very simple retry algorithm is employed, no complex arbitration is needed, and the arbitration circuit at the crosspoint can be reduced by about 90% in size. The proposed ATM switch architecture is applicable to high-speed (Gbit/s) ATM switches for B-ISDN because of its simplicity.
|Number of pages||5|
|Journal||IEICE Transactions on Communications|
|Publication status||Published - 1993 Jul 1|
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering