High-speed ATM switching architecture using small shared switch blocks

Ken ichi Endo, Naoaki Yamanaka

Research output: Contribution to journalArticle

Abstract

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The N × N matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N-2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

Original languageEnglish
Pages (from-to)736-740
Number of pages5
JournalIEICE Transactions on Communications
VolumeE76-B
Issue number7
Publication statusPublished - 1993 Jul
Externally publishedYes

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Automatic teller machines
Switches
Voice/data communication systems
Computer simulation

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

High-speed ATM switching architecture using small shared switch blocks. / Endo, Ken ichi; Yamanaka, Naoaki.

In: IEICE Transactions on Communications, Vol. E76-B, No. 7, 07.1993, p. 736-740.

Research output: Contribution to journalArticle

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