High-speed decompression architecture of compressed HTTP streams for the internet routers

Hironori Okano, Hayato Yamaki, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In recent years, studies of DPI have been carried out actively. HTTP packets, which are a kind of DPI target, include GZIP compressed packets, and multi-streamed GZIP compressed HTTP cannot be analyzed directly on routers. Moreover, wire-rate processing is required to achieve on-router analysis. In this paper, HTTP decompressing architecture on routers supporting 40Gbps network is considered, and three mechanisms, which are parallelized architecture, cache architecture and piggy-back method, were proposed for achieving higher throughput. Hardware cost simulations by using Verilog HDL confirms it can achieve 10Gbps throughput at low circuit costs.

Original languageEnglish
Title of host publication2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages31-36
Number of pages6
ISBN (Electronic)9781509013593
DOIs
Publication statusPublished - 2016 Jul 20
Event2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016 - Hamburg, Germany
Duration: 2016 May 92016 May 10

Other

Other2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016
CountryGermany
CityHamburg
Period16/5/916/5/10

Fingerprint

HTTP
Routers
Internet
Throughput
Computer hardware description languages
Costs
Wire
Hardware
Networks (circuits)
Processing

Keywords

  • GZIP Decompression
  • HTTP compression
  • Network Router
  • Parallel Processing

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Okano, H., Yamaki, H., & Nishi, H. (2016). High-speed decompression architecture of compressed HTTP streams for the internet routers. In 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016 (pp. 31-36). [7518531] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPGA4GPC.2016.7518531

High-speed decompression architecture of compressed HTTP streams for the internet routers. / Okano, Hironori; Yamaki, Hayato; Nishi, Hiroaki.

2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 31-36 7518531.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Okano, H, Yamaki, H & Nishi, H 2016, High-speed decompression architecture of compressed HTTP streams for the internet routers. in 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016., 7518531, Institute of Electrical and Electronics Engineers Inc., pp. 31-36, 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016, Hamburg, Germany, 16/5/9. https://doi.org/10.1109/FPGA4GPC.2016.7518531
Okano H, Yamaki H, Nishi H. High-speed decompression architecture of compressed HTTP streams for the internet routers. In 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 31-36. 7518531 https://doi.org/10.1109/FPGA4GPC.2016.7518531
Okano, Hironori ; Yamaki, Hayato ; Nishi, Hiroaki. / High-speed decompression architecture of compressed HTTP streams for the internet routers. 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing, FPGA4GPC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 31-36
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