High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Tetsu Nagamatu, Shinichi Yoshioka, Toshikazu Sei, Kenji Matsuo, Yoichiro Hamura, Toshiaki Mori, Masayuki Murota, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Citations (Scopus)

Abstract

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherIEEE
Pages53-56
Number of pages4
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 1996 May 51996 May 8

Other

OtherProceedings of the 1996 IEEE Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period96/5/596/5/8

Fingerprint

Threshold voltage
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kuroda, T., Fujita, T., Nagamatu, T., Yoshioka, S., Sei, T., Matsuo, K., ... Sakurai, T. (1996). High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. In Proceedings of the Custom Integrated Circuits Conference (pp. 53-56). IEEE.

High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Nagamatu, Tetsu; Yoshioka, Shinichi; Sei, Toshikazu; Matsuo, Kenji; Hamura, Yoichiro; Mori, Toshiaki; Murota, Masayuki; Kakumu, Masakazu; Sakurai, Takayasu.

Proceedings of the Custom Integrated Circuits Conference. IEEE, 1996. p. 53-56.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuroda, T, Fujita, T, Nagamatu, T, Yoshioka, S, Sei, T, Matsuo, K, Hamura, Y, Mori, T, Murota, M, Kakumu, M & Sakurai, T 1996, High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. in Proceedings of the Custom Integrated Circuits Conference. IEEE, pp. 53-56, Proceedings of the 1996 IEEE Custom Integrated Circuits Conference, San Diego, CA, USA, 96/5/5.
Kuroda T, Fujita T, Nagamatu T, Yoshioka S, Sei T, Matsuo K et al. High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. In Proceedings of the Custom Integrated Circuits Conference. IEEE. 1996. p. 53-56
Kuroda, Tadahiro ; Fujita, Tetsuya ; Nagamatu, Tetsu ; Yoshioka, Shinichi ; Sei, Toshikazu ; Matsuo, Kenji ; Hamura, Yoichiro ; Mori, Toshiaki ; Murota, Masayuki ; Kakumu, Masakazu ; Sakurai, Takayasu. / High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme. Proceedings of the Custom Integrated Circuits Conference. IEEE, 1996. pp. 53-56
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AU - Sei, Toshikazu

AU - Matsuo, Kenji

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AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

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