High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Tetsu Nagamatu, Shinichi Yoshioka, Toshikazu Sei, Kenji Matsuo, Yoichiro Hamura, Toshiaki Mori, Masayuki Murota, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journalConference articlepeer-review

35 Citations (Scopus)

Abstract

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

Original languageEnglish
Pages (from-to)53-56
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1996 Jan 1
Externally publishedYes
EventProceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 1996 May 51996 May 8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'High-speed low-power 0.3μm CMOS gate array with variable threshold voltage (VT) scheme'. Together they form a unique fingerprint.

Cite this