Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3μm CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA|
Duration: 1996 May 5 → 1996 May 8
ASJC Scopus subject areas
- Electrical and Electronic Engineering