High-speed, low-power emitter coupled logic circuits

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

Original languageEnglish
Title of host publicationDigital Design and Fabrication
PublisherCRC Press
Pages3-1-3-16
ISBN (Electronic)9780849386046
ISBN (Print)9780849386022
DOIs
Publication statusPublished - 2017 Jan 1

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Emitter coupled logic circuits
VLSI circuits
Electric potential
Energy dissipation
Switches
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Cite this

Kuroda, T. (2017). High-speed, low-power emitter coupled logic circuits. In Digital Design and Fabrication (pp. 3-1-3-16). CRC Press. https://doi.org/10.1201/9780849386046

High-speed, low-power emitter coupled logic circuits. / Kuroda, Tadahiro.

Digital Design and Fabrication. CRC Press, 2017. p. 3-1-3-16.

Research output: Chapter in Book/Report/Conference proceedingChapter

Kuroda, T 2017, High-speed, low-power emitter coupled logic circuits. in Digital Design and Fabrication. CRC Press, pp. 3-1-3-16. https://doi.org/10.1201/9780849386046
Kuroda T. High-speed, low-power emitter coupled logic circuits. In Digital Design and Fabrication. CRC Press. 2017. p. 3-1-3-16 https://doi.org/10.1201/9780849386046
Kuroda, Tadahiro. / High-speed, low-power emitter coupled logic circuits. Digital Design and Fabrication. CRC Press, 2017. pp. 3-1-3-16
@inbook{e60f2ab7dc9343ae92b412a31df44516,
title = "High-speed, low-power emitter coupled logic circuits",
abstract = "Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.",
author = "Tadahiro Kuroda",
year = "2017",
month = "1",
day = "1",
doi = "10.1201/9780849386046",
language = "English",
isbn = "9780849386022",
pages = "3--1--3--16",
booktitle = "Digital Design and Fabrication",
publisher = "CRC Press",

}

TY - CHAP

T1 - High-speed, low-power emitter coupled logic circuits

AU - Kuroda, Tadahiro

PY - 2017/1/1

Y1 - 2017/1/1

N2 - Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

AB - Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

UR - http://www.scopus.com/inward/record.url?scp=85052569790&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85052569790&partnerID=8YFLogxK

U2 - 10.1201/9780849386046

DO - 10.1201/9780849386046

M3 - Chapter

AN - SCOPUS:85052569790

SN - 9780849386022

SP - 3-1-3-16

BT - Digital Design and Fabrication

PB - CRC Press

ER -