High-speed, low-power emitter coupled logic circuits

Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Abstract

    Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pull-down transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

    Original languageEnglish
    Title of host publicationDigital Design and Fabrication
    PublisherCRC Press
    Pages3-1-3-16
    ISBN (Electronic)9780849386046
    ISBN (Print)9780849386022
    DOIs
    Publication statusPublished - 2017 Jan 1

    ASJC Scopus subject areas

    • Computer Science(all)
    • Engineering(all)

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  • Cite this

    Kuroda, T. (2017). High-speed, low-power emitter coupled logic circuits. In Digital Design and Fabrication (pp. 3-1-3-16). CRC Press. https://doi.org/10.1201/9780849386046