High-speed, low-power emitter coupled logic circuits

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

Original languageEnglish
Title of host publicationThe Computer Engineering Handbook
PublisherCRC Press
Pages3-1-3-15
ISBN (Electronic)9781420041545
ISBN (Print)9780849308857
Publication statusPublished - 2001 Jan 1

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Emitter coupled logic circuits
VLSI circuits
Electric potential
Energy dissipation
Switches
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Kuroda, T. (2001). High-speed, low-power emitter coupled logic circuits. In The Computer Engineering Handbook (pp. 3-1-3-15). CRC Press.

High-speed, low-power emitter coupled logic circuits. / Kuroda, Tadahiro.

The Computer Engineering Handbook. CRC Press, 2001. p. 3-1-3-15.

Research output: Chapter in Book/Report/Conference proceedingChapter

Kuroda, T 2001, High-speed, low-power emitter coupled logic circuits. in The Computer Engineering Handbook. CRC Press, pp. 3-1-3-15.
Kuroda T. High-speed, low-power emitter coupled logic circuits. In The Computer Engineering Handbook. CRC Press. 2001. p. 3-1-3-15
Kuroda, Tadahiro. / High-speed, low-power emitter coupled logic circuits. The Computer Engineering Handbook. CRC Press, 2001. pp. 3-1-3-15
@inbook{d9856bdfc9ec441186abbb9034c32b59,
title = "High-speed, low-power emitter coupled logic circuits",
abstract = "Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.",
author = "Tadahiro Kuroda",
year = "2001",
month = "1",
day = "1",
language = "English",
isbn = "9780849308857",
pages = "3--1--3--15",
booktitle = "The Computer Engineering Handbook",
publisher = "CRC Press",

}

TY - CHAP

T1 - High-speed, low-power emitter coupled logic circuits

AU - Kuroda, Tadahiro

PY - 2001/1/1

Y1 - 2001/1/1

N2 - Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

AB - Emitter-coupled logic (ECL) circuits have often been employed in very high-speed VLSI circuits. However, a passive pull-down scheme in an output stage results in high power dissipation as well as slow pulldown transition. Gate stacking in a current switch logic stage keeps ECL circuits from operating at low power supply voltages. In this section, a high-speed active pull-down scheme in the output stage, as well as a low-voltage series-gating scheme in the logic stage will be presented. The two circuit techniques can be employed together to obtain multiple effects in terms of speed and power.

UR - http://www.scopus.com/inward/record.url?scp=85056401988&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85056401988&partnerID=8YFLogxK

M3 - Chapter

SN - 9780849308857

SP - 3-1-3-15

BT - The Computer Engineering Handbook

PB - CRC Press

ER -