High-Speed Time Division Switch for 32-Mbit/s Bearer Rate Signals

Naoaki Yamanaka, Hiroshi Miyanaga, Yousuke Yamamoto

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper describes the high-speed time division switch employed in a 32-Mbit/s bearer signal communications system. System performance is realized by using three technologies. The first is a switch structure referred to as a 2-RAM 2-bank structure which ensures high-speed performance by increasing switching throughput four times over that of the basic structure. The second is the inclusion in the switch of two types of peripheral logic developed using Si-bipolar super-self-aligned process technology. The third is high-speed synchronous transmission of data. A large channel capacity time division switching network is also discussed. In conjunction with the network, these technologies make it possible to realize the ISDN time division switches necessary for such services as TV and high-definition TV communications.

Original languageEnglish
Pages (from-to)1249-1255
Number of pages7
JournalIEEE Journal on Selected Areas in Communications
Volume5
Issue number8
DOIs
Publication statusPublished - 1987 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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