HIGH-SPEED TIME DIVISION SWITCH OPERATING AT 256Mb/s.

Naoaki Yamanaka, Masaharu Kawakami, Yasukazu Terada

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s multiplied by 64 channels) are obtained.

Original languageEnglish
Pages (from-to)570-571
Number of pages2
JournalTransactions of the Institute of Electronics and Communication Engineers of Japan. Section E
VolumeE68
Issue number9
Publication statusPublished - 1985 Sep
Externally publishedYes

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Switches
Emitter coupled logic circuits
Switching systems
Random access storage
Throughput

ASJC Scopus subject areas

  • Engineering(all)

Cite this

HIGH-SPEED TIME DIVISION SWITCH OPERATING AT 256Mb/s. / Yamanaka, Naoaki; Kawakami, Masaharu; Terada, Yasukazu.

In: Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E, Vol. E68, No. 9, 09.1985, p. 570-571.

Research output: Contribution to journalArticle

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