This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s multiplied by 64 channels) are obtained.
|Number of pages||2|
|Journal||Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E|
|Publication status||Published - 1985 Sep 1|
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