Abstract
This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s multiplied by 64 channels) are obtained.
| Original language | English |
|---|---|
| Pages (from-to) | 570-571 |
| Number of pages | 2 |
| Journal | Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E |
| Volume | E68 |
| Issue number | 9 |
| Publication status | Published - 1985 Sept 1 |
| Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)