Highlights of the isscc 2013 processors and high performance digital sessions

Timothy Fischer, Byeong Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A.P. Pertijs

    Research output: Contribution to journalReview article

    Abstract

    The IEEE International Solid-State Circuits Conference (ISSCC) is the foremost global forum for presenting advances in solid-state circuits and systems-on-a-chip. Every year since its first issue, the IEEE JOURNAL OF SOLID-STATE CIRCUITS has highlighted some well-received papers from the most recent ISSCC in special issues. The 1.14 B transistor design includes eight 4-issue out-of-order CPUs, shared 8 MB L3 cache, two-levels of on-chip interconnect, DDR controller, four core supplies, and on-board power management. The paper describes design challenges and methodology used in scaling the design from a 65 nm bulk technology to 32 nm and 28 nm processes. Four highly innovative papers were selected from the Energy Efficient Digital sessions at ISSCC 2013. These papers detail some of the leading-edge advancements in energy-efficient digital circuit techniques.

    Original languageEnglish
    Article number6690153
    Pages (from-to)4-8
    Number of pages5
    JournalIEEE Journal of Solid-State Circuits
    Volume49
    Issue number1
    DOIs
    Publication statusPublished - 2014 Jan 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Fischer, T., Nam, B. G., Chang, L., Kuroda, T., & Pertijs, M. A. P. (2014). Highlights of the isscc 2013 processors and high performance digital sessions. IEEE Journal of Solid-State Circuits, 49(1), 4-8. [6690153]. https://doi.org/10.1109/JSSC.2013.2284658