Implementation and evaluation of a high speed license plate recognition system on an FPGA

Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against danger of collision to measure distance to a licence plate of a proceeding car. This paper proposes a high speed FPGA off-loading engine for detecting the licence plate. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature; 100 frames per second; can be achieved even though extra computation time on an embedded processor and communication time with it are considered.

Original languageEnglish
Title of host publicationCIT 2007: 7th IEEE International Conference on Computer and Information Technology
Pages567-572
Number of pages6
DOIs
Publication statusPublished - 2007
EventCIT 2007: 7th IEEE International Conference on Computer and Information Technology - Aizu-Wakamatsu, Fukushima, Japan
Duration: 2007 Oct 162007 Oct 19

Other

OtherCIT 2007: 7th IEEE International Conference on Computer and Information Technology
CountryJapan
CityAizu-Wakamatsu, Fukushima
Period07/10/1607/10/19

Fingerprint

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
High Speed
Embedded Processor
Highway accidents
Evaluation
Distributed Memory
Distance Measure
Processing
Parallel Processing
Accidents
Driver
Image Processing
Image processing
Engine
Railroad cars
Collision
High Performance
Pipelines
Safety

Keywords

  • Dynamically reconfigurable processor
  • Multiprocessing execution
  • Single-processing execution

ASJC Scopus subject areas

  • Computer Science Applications
  • Information Systems
  • Software
  • Mathematics(all)

Cite this

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T., & Ajioka, Y. (2007). Implementation and evaluation of a high speed license plate recognition system on an FPGA. In CIT 2007: 7th IEEE International Conference on Computer and Information Technology (pp. 567-572). [4385143] https://doi.org/10.1109/CIT.2007.4385143

Implementation and evaluation of a high speed license plate recognition system on an FPGA. / Kanamori, Takamasa; Amano, Hideharu; Arai, Masatoshi; Konno, Daisuke; Nanba, Tomomichi; Ajioka, Yoshiaki.

CIT 2007: 7th IEEE International Conference on Computer and Information Technology. 2007. p. 567-572 4385143.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kanamori, T, Amano, H, Arai, M, Konno, D, Nanba, T & Ajioka, Y 2007, Implementation and evaluation of a high speed license plate recognition system on an FPGA. in CIT 2007: 7th IEEE International Conference on Computer and Information Technology., 4385143, pp. 567-572, CIT 2007: 7th IEEE International Conference on Computer and Information Technology, Aizu-Wakamatsu, Fukushima, Japan, 07/10/16. https://doi.org/10.1109/CIT.2007.4385143
Kanamori T, Amano H, Arai M, Konno D, Nanba T, Ajioka Y. Implementation and evaluation of a high speed license plate recognition system on an FPGA. In CIT 2007: 7th IEEE International Conference on Computer and Information Technology. 2007. p. 567-572. 4385143 https://doi.org/10.1109/CIT.2007.4385143
Kanamori, Takamasa ; Amano, Hideharu ; Arai, Masatoshi ; Konno, Daisuke ; Nanba, Tomomichi ; Ajioka, Yoshiaki. / Implementation and evaluation of a high speed license plate recognition system on an FPGA. CIT 2007: 7th IEEE International Conference on Computer and Information Technology. 2007. pp. 567-572
@inproceedings{3d745f7a19f947fe88b9b4a14ab90661,
title = "Implementation and evaluation of a high speed license plate recognition system on an FPGA",
abstract = "In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against danger of collision to measure distance to a licence plate of a proceeding car. This paper proposes a high speed FPGA off-loading engine for detecting the licence plate. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature; 100 frames per second; can be achieved even though extra computation time on an embedded processor and communication time with it are considered.",
keywords = "Dynamically reconfigurable processor, Multiprocessing execution, Single-processing execution",
author = "Takamasa Kanamori and Hideharu Amano and Masatoshi Arai and Daisuke Konno and Tomomichi Nanba and Yoshiaki Ajioka",
year = "2007",
doi = "10.1109/CIT.2007.4385143",
language = "English",
isbn = "0769529836",
pages = "567--572",
booktitle = "CIT 2007: 7th IEEE International Conference on Computer and Information Technology",

}

TY - GEN

T1 - Implementation and evaluation of a high speed license plate recognition system on an FPGA

AU - Kanamori, Takamasa

AU - Amano, Hideharu

AU - Arai, Masatoshi

AU - Konno, Daisuke

AU - Nanba, Tomomichi

AU - Ajioka, Yoshiaki

PY - 2007

Y1 - 2007

N2 - In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against danger of collision to measure distance to a licence plate of a proceeding car. This paper proposes a high speed FPGA off-loading engine for detecting the licence plate. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature; 100 frames per second; can be achieved even though extra computation time on an embedded processor and communication time with it are considered.

AB - In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against danger of collision to measure distance to a licence plate of a proceeding car. This paper proposes a high speed FPGA off-loading engine for detecting the licence plate. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature; 100 frames per second; can be achieved even though extra computation time on an embedded processor and communication time with it are considered.

KW - Dynamically reconfigurable processor

KW - Multiprocessing execution

KW - Single-processing execution

UR - http://www.scopus.com/inward/record.url?scp=38049013334&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=38049013334&partnerID=8YFLogxK

U2 - 10.1109/CIT.2007.4385143

DO - 10.1109/CIT.2007.4385143

M3 - Conference contribution

AN - SCOPUS:38049013334

SN - 0769529836

SN - 9780769529837

SP - 567

EP - 572

BT - CIT 2007: 7th IEEE International Conference on Computer and Information Technology

ER -