Implementation and evaluation of fine-grain run-time power gating for a multiplier

Kimiyoshi Usami, Mitsutaka Nakata, Toshiaki Shirai, Seidai Takeda, Naomi Seki, Hideharu Amano, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In a 32bx32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32bx32b multiplier and implementing in a commercial 90nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25°C to 10 cycles at 65°C and to 3 cycles at 100°C at 100MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65°C and by 39% at 100°C over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25°C. The ground bounce at the wakeup was effectively suppressed to 91mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44ns.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages7-10
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States
Duration: 2009 May 182009 May 20

Publication series

Name2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Other

Other2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
CountryUnited States
CityAustin, TX
Period09/5/1809/5/20

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H., & Nakamura, H. (2009). Implementation and evaluation of fine-grain run-time power gating for a multiplier. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 7-10). [5166253] (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166253