Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyasiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DIMMnet-2 is a network interface for PC cluster, plugged into a DIMM slot. Connecting network interface into commonly used memory bus reduces the cost of building PC cluster compared with using expensive machines with recent high performance I/O bus like PCIX. Moreover, low latency communication from the host CPU can be achieved. In this paper, implementation of the mechanisms for low latency communication on the DIMMnet-2 prototype board by making the best use of the memory slot is shown. Its latency for 4 Bytes data transfer is only 1.4 μs which is lower than those of InfiniBand and QsNET II on condition those host processes are Intel Xeon.

Original languageEnglish
Title of host publicationHigh-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers
Pages211-218
Number of pages8
Publication statusPublished - 2008 Feb 1
Event6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006 - Nara, Japan
Duration: 2005 Sep 72005 Sep 9

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4759 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other6th International Symposium on High Performance Computing, ISHPC 2005 and 1st International Workshop on Advanced Low Power Systems, ALPS 2006
CountryJapan
CityNara
Period05/9/705/9/9

Keywords

  • DIMMnet-2
  • Network interface
  • PC cluster

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H., & Amano, H. (2008). Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2. In High-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers (pp. 211-218). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4759 LNCS).