The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|Publication status||Published - 1986 Dec 1|
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering