IMPLEMENTATION OF A NEW TYPE DSP PLL USING HIGH PERFORMANCE DSP DSSP-1.

S. Ono, T. Aoyama, M. Hagiwara, M. Nakagawa

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

The authors describe a new digital processing phase lock loop (PLL) implemented on the DSSP 1 high-performance digital signal processor. The new PLL has linear phase comparison characteristics and is called the linear digital PLL. It exhibits fast acquisition without an increase in jitter, its pull-in range is wider, and its steady-state errors and sampling frequency are lower than those of conventional PLLs. It also does not require automatic gain control.

Original languageEnglish
Pages (from-to)2195-2198
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 1986 Dec 1
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

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