Implementation of super high definition image processing on HiPIPE

Tetsurou Fujii, Tomoko Sawabe, Naohisa Ohta, Sadayasu Ono

Research output: Contribution to journalConference article

Abstract

In order to manipulate SHD (super high definition) images, a novel parallel processing unit called HiPIPE (Highly Parallel Image Processing Engine) is developed as a project of NOVI-II. The engine is connected to an SHD image display unit and an image data storage unit. Extremely high computational power is obtained by a multicomputer type parallel processing technique. 128 processing elements are connected by a mesh network. Various image coding schemes are carefully explored from the viewpoint of parallel processing, and the problem of processor connections is examined. A novel load-balancing technique, called 2-dimensional butterfly data shuffling, is developed and implemented. The current version of HiPIPE uses just 128 scaler processing elements and has more than twice the power of a single-processor CRAY-2 for a still SHD image coding task.

Original languageEnglish
Pages (from-to)348-351
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 1991 Dec 1
Event1991 IEEE International Symposium on Circuits and Systems Part 1 (of 5) - Singapore, Singapore
Duration: 1991 Jun 111991 Jun 14

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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