TY - GEN
T1 - Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System
AU - Ito, Kohei
AU - Iizuka, Kensuke
AU - Hironaka, Kazuei
AU - Hu, Yao
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
N1 - Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2020/11
Y1 - 2020/11
N2 - A multi-FPGA System called Flow-in-Cloud (FiC) is currently being developed as an accelerator of Multi-access Edge Computing (MEC), which is one of the core 5G technologies. FiC is a system that consists of multiple mid-range FPGAs tightly connected by high-speed serial links. Since timing-critical jobs are assumed to be executed in MEC, a circuit-switched network with static time-division multiplexing (STDM) switches has been implemented on FiC. In this paper, we investigate the methods to enhance the interconnection performance of FiC. We proposed the link aggregation and the slot distribution for making the use of multiple lanes naturally supported with Aurora-IP and economical FireFly cables. We evaluated combinations of the techniques by using three practical applications on a real FiC prototype with 24 boards. When the number of slots is large and the number of packets is small, the slot distribution is sometimes more effective, while the link aggregation is superior for other most cases. As a result, the communication performance could be improved up to 3.01 times by using four lanes. Furthermore, we found that application designers can use enough resources even using four lanes and the link aggregation is better than the slot distribution.
AB - A multi-FPGA System called Flow-in-Cloud (FiC) is currently being developed as an accelerator of Multi-access Edge Computing (MEC), which is one of the core 5G technologies. FiC is a system that consists of multiple mid-range FPGAs tightly connected by high-speed serial links. Since timing-critical jobs are assumed to be executed in MEC, a circuit-switched network with static time-division multiplexing (STDM) switches has been implemented on FiC. In this paper, we investigate the methods to enhance the interconnection performance of FiC. We proposed the link aggregation and the slot distribution for making the use of multiple lanes naturally supported with Aurora-IP and economical FireFly cables. We evaluated combinations of the techniques by using three practical applications on a real FiC prototype with 24 boards. When the number of slots is large and the number of packets is small, the slot distribution is sometimes more effective, while the link aggregation is superior for other most cases. As a result, the communication performance could be improved up to 3.01 times by using four lanes. Furthermore, we found that application designers can use enough resources even using four lanes and the link aggregation is better than the slot distribution.
KW - circuit-switched network
KW - multi-FPGA
KW - multi-FPGA communication
KW - static time-division multiplexing switch
KW - STDM switch
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U2 - 10.1109/CANDARW51189.2020.00049
DO - 10.1109/CANDARW51189.2020.00049
M3 - Conference contribution
AN - SCOPUS:85097876625
T3 - Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
SP - 211
EP - 217
BT - Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th International Symposium on Computing and Networking Workshops, CANDARW 2020
Y2 - 24 November 2020 through 27 November 2020
ER -