Implementing and evaluating stream applications on the dynamically reconfigurable processor

Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Tom Awashima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Dynamically Recon gurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain recon gurable processor that selects a data path from the on-chip repository of sixteen circuit con gurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the rst prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on recon gurable processors and discuss their feasibility in boosting system performance.

Original languageEnglish
Title of host publicationProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
EditorsJ. Arnold, K.L. Pocek
Pages328-329
Number of pages2
DOIs
Publication statusPublished - 2004
EventProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 - Napa, CA, United States
Duration: 2004 Apr 202004 Apr 23

Other

OtherProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
CountryUnited States
CityNapa, CA
Period04/4/2004/4/23

Fingerprint

Program processors
Electronic equipment
Data storage equipment
Networks (circuits)
Processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, N., Kurotaki, S., Suzuki, M., Kaneko, N., Yamada, Y., Deguchi, K., ... Awashima, T. (2004). Implementing and evaluating stream applications on the dynamically reconfigurable processor. In J. Arnold, & K. L. Pocek (Eds.), Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 (pp. 328-329) https://doi.org/10.1109/FCCM.2004.42

Implementing and evaluating stream applications on the dynamically reconfigurable processor. / Suzuki, Noriaki; Kurotaki, Shunsuke; Suzuki, Masayasu; Kaneko, Naoto; Yamada, Yutaka; Deguchi, Katsuaki; Hasegawa, Yohei; Amano, Hideharu; Anjo, Kenichiro; Motomura, Masato; Wakabayashi, Kazutoshi; Toi, Takeo; Awashima, Tom.

Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. ed. / J. Arnold; K.L. Pocek. 2004. p. 328-329.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, N, Kurotaki, S, Suzuki, M, Kaneko, N, Yamada, Y, Deguchi, K, Hasegawa, Y, Amano, H, Anjo, K, Motomura, M, Wakabayashi, K, Toi, T & Awashima, T 2004, Implementing and evaluating stream applications on the dynamically reconfigurable processor. in J Arnold & KL Pocek (eds), Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. pp. 328-329, Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004, Napa, CA, United States, 04/4/20. https://doi.org/10.1109/FCCM.2004.42
Suzuki N, Kurotaki S, Suzuki M, Kaneko N, Yamada Y, Deguchi K et al. Implementing and evaluating stream applications on the dynamically reconfigurable processor. In Arnold J, Pocek KL, editors, Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. 2004. p. 328-329 https://doi.org/10.1109/FCCM.2004.42
Suzuki, Noriaki ; Kurotaki, Shunsuke ; Suzuki, Masayasu ; Kaneko, Naoto ; Yamada, Yutaka ; Deguchi, Katsuaki ; Hasegawa, Yohei ; Amano, Hideharu ; Anjo, Kenichiro ; Motomura, Masato ; Wakabayashi, Kazutoshi ; Toi, Takeo ; Awashima, Tom. / Implementing and evaluating stream applications on the dynamically reconfigurable processor. Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. editor / J. Arnold ; K.L. Pocek. 2004. pp. 328-329
@inproceedings{905160e804304ab1b8c1268a0dce1b12,
title = "Implementing and evaluating stream applications on the dynamically reconfigurable processor",
abstract = "Dynamically Recon gurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain recon gurable processor that selects a data path from the on-chip repository of sixteen circuit con gurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the rst prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on recon gurable processors and discuss their feasibility in boosting system performance.",
author = "Noriaki Suzuki and Shunsuke Kurotaki and Masayasu Suzuki and Naoto Kaneko and Yutaka Yamada and Katsuaki Deguchi and Yohei Hasegawa and Hideharu Amano and Kenichiro Anjo and Masato Motomura and Kazutoshi Wakabayashi and Takeo Toi and Tom Awashima",
year = "2004",
doi = "10.1109/FCCM.2004.42",
language = "English",
isbn = "0769522300",
pages = "328--329",
editor = "J. Arnold and K.L. Pocek",
booktitle = "Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004",

}

TY - GEN

T1 - Implementing and evaluating stream applications on the dynamically reconfigurable processor

AU - Suzuki, Noriaki

AU - Kurotaki, Shunsuke

AU - Suzuki, Masayasu

AU - Kaneko, Naoto

AU - Yamada, Yutaka

AU - Deguchi, Katsuaki

AU - Hasegawa, Yohei

AU - Amano, Hideharu

AU - Anjo, Kenichiro

AU - Motomura, Masato

AU - Wakabayashi, Kazutoshi

AU - Toi, Takeo

AU - Awashima, Tom

PY - 2004

Y1 - 2004

N2 - Dynamically Recon gurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain recon gurable processor that selects a data path from the on-chip repository of sixteen circuit con gurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the rst prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on recon gurable processors and discuss their feasibility in boosting system performance.

AB - Dynamically Recon gurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain recon gurable processor that selects a data path from the on-chip repository of sixteen circuit con gurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the rst prototype chip, and evaluation results are presented. By computing parallelly using the Processing Elements(PEs) and distributed memory modules, DRP-1 out-performed Pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on recon gurable processors and discuss their feasibility in boosting system performance.

UR - http://www.scopus.com/inward/record.url?scp=20844445313&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20844445313&partnerID=8YFLogxK

U2 - 10.1109/FCCM.2004.42

DO - 10.1109/FCCM.2004.42

M3 - Conference contribution

AN - SCOPUS:20844445313

SN - 0769522300

SN - 9780769522302

SP - 328

EP - 329

BT - Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

A2 - Arnold, J.

A2 - Pocek, K.L.

ER -