TY - GEN
T1 - In-switch approximate processing
T2 - 27th International Conference on Field Programmable Logic and Applications, FPL 2017
AU - Mitsuzuka, Koya
AU - Hayashi, Ami
AU - Koibuchi, Michihiro
AU - Amano, Hideharu
AU - Matsutani, Hiroki
N1 - Funding Information:
Acknowledgements This work was supported by JSPS KAK-ENHI Grant Number JP16H02816 and SECOM Science and Technology Foundation.
Publisher Copyright:
© 2017 Ghent University.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/10/2
Y1 - 2017/10/2
N2 - In MapReduce, the parallel processing performance is often limited by only a few compute nodes that delay to complete given tasks. Although various techniques have been invented to handle such stragglers, these techniques mostly impose a burden on master node to monitor the progress of all the compute nodes, resulting in a new bottleneck as the number of compute nodes increases. As an alternative approach, in this paper, we propose to move such straggler management burden from master node to network switch that connects the master and compute nodes, because all the information goes through the switch. More specifically, the proposed network switch monitors output packets from Map tasks to detect stragglers. When detected, the proposed switch generates a response instead of the straggler based on the outputs of the other normal Map tasks, so that Reduce tasks can be started without delay. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called 'ApproxSW.' We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. An experiment shows that the ApproxSW functions do not degrade the original 10GbE switch performance. We also analyze the accuracy of the proxy computation and response for stragglers and show that the proposed approximation based on task similarity achieves the best accuracy.
AB - In MapReduce, the parallel processing performance is often limited by only a few compute nodes that delay to complete given tasks. Although various techniques have been invented to handle such stragglers, these techniques mostly impose a burden on master node to monitor the progress of all the compute nodes, resulting in a new bottleneck as the number of compute nodes increases. As an alternative approach, in this paper, we propose to move such straggler management burden from master node to network switch that connects the master and compute nodes, because all the information goes through the switch. More specifically, the proposed network switch monitors output packets from Map tasks to detect stragglers. When detected, the proposed switch generates a response instead of the straggler based on the outputs of the other normal Map tasks, so that Reduce tasks can be started without delay. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called 'ApproxSW.' We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. An experiment shows that the ApproxSW functions do not degrade the original 10GbE switch performance. We also analyze the accuracy of the proxy computation and response for stragglers and show that the proposed approximation based on task similarity achieves the best accuracy.
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U2 - 10.23919/FPL.2017.8056802
DO - 10.23919/FPL.2017.8056802
M3 - Conference contribution
AN - SCOPUS:85034443526
T3 - 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
BT - 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
A2 - Gohringer, Diana
A2 - Stroobandt, Dirk
A2 - Mentens, Nele
A2 - Santambrogio, Marco
A2 - Nurmi, Jari
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 September 2017 through 6 September 2017
ER -