Instruction buffer mode for multi-context dynamically reconfigurable processors

Torn Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose anew execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory is stored in the instruction buffer and executed directly. Furthermore, by exploiting a multicast method, a single configuration code loaded to the buffer can be executed by multiple processing elements in a SIMD fashion. We also investigate a mode selection policy based on simple formulas. From the result of implementation and evaluation by using a prototype DRPA called MuCCRA-1, it appears that the total execution time is reduced 12% by using the instruction buffer mode, while 12% of the semiconductor area is increased.

Original languageEnglish
Title of host publicationProceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Pages215-220
Number of pages6
DOIs
Publication statusPublished - 2008
Event2008 International Conference on Field Programmable Logic and Applications, FPL - Heidelberg, Germany
Duration: 2008 Sep 82008 Sep 10

Other

Other2008 International Conference on Field Programmable Logic and Applications, FPL
CountryGermany
CityHeidelberg
Period08/9/808/9/10

Fingerprint

Parallel processing systems
Data storage equipment
Semiconductor materials
Processing

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Sano, T., Kato, M., Tsutsumi, S., Hasegawa, Y., & Amano, H. (2008). Instruction buffer mode for multi-context dynamically reconfigurable processors. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL (pp. 215-220). [4629934] https://doi.org/10.1109/FPL.2008.4629934

Instruction buffer mode for multi-context dynamically reconfigurable processors. / Sano, Torn; Kato, Masaru; Tsutsumi, Satoshi; Hasegawa, Yohei; Amano, Hideharu.

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 215-220 4629934.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sano, T, Kato, M, Tsutsumi, S, Hasegawa, Y & Amano, H 2008, Instruction buffer mode for multi-context dynamically reconfigurable processors. in Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL., 4629934, pp. 215-220, 2008 International Conference on Field Programmable Logic and Applications, FPL, Heidelberg, Germany, 08/9/8. https://doi.org/10.1109/FPL.2008.4629934
Sano T, Kato M, Tsutsumi S, Hasegawa Y, Amano H. Instruction buffer mode for multi-context dynamically reconfigurable processors. In Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. p. 215-220. 4629934 https://doi.org/10.1109/FPL.2008.4629934
Sano, Torn ; Kato, Masaru ; Tsutsumi, Satoshi ; Hasegawa, Yohei ; Amano, Hideharu. / Instruction buffer mode for multi-context dynamically reconfigurable processors. Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. 2008. pp. 215-220
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