Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    25 Citations (Scopus)

    Abstract

    This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller than that for high-performance applications (mesh type). Interference from signal lines requires only 9% of additional transmit power even in the worst case of logic circuits. In typical operation range, interference to SRAM is ignorable. Only when supply voltage is much lower than typical range, the bit-line noise from the inductive-coupling link influences SRAM operation. Interference to SRAM is small compared with other influences such as device variations and soft errors.

    Original languageEnglish
    Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
    Pages131-134
    Number of pages4
    DOIs
    Publication statusPublished - 2007 Dec 1
    Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
    Duration: 2007 Nov 122007 Nov 14

    Publication series

    Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

    Other

    Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
    CountryKorea, Republic of
    CityJeju
    Period07/11/1207/11/14

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Fingerprint Dive into the research topics of 'Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link'. Together they form a unique fingerprint.

  • Cite this

    Niitsu, K., Sugimori, Y., Kohama, Y., Osada, K., Irie, N., Ishikuro, H., & Kuroda, T. (2007). Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 131-134). [4425749] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425749