I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique

Masaki Yonekura, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a new technique to suppress I/Q mismatch and decrease power consumption and chip area. The proposed technique uses two methods for all integrators and DAC in the modulator which are main sources of the mismatch and power. One is proposed ternary capacitor rotation technique to compensate the I/Q mismatch and achieve high image-rejection. The other is amplifier-sharing technique to reduce the number of amplifier and power consumption. The third-order 1bit delta-sigma modulator was designed in 65nm CMOS process, and fabricated test chip achieved an image-rejection ratio (IRR) of higher than 70dB throughout a 1MHz bandwidth. The overall power consumption is 12.7mW including I/Q channels.

Original languageEnglish
Title of host publicationEuropean Solid-State Circuits Conference
PublisherIEEE Computer Society
Pages229-232
Number of pages4
Volume2015-October
ISBN (Print)9781467374705
DOIs
Publication statusPublished - 2015 Oct 30
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 2015 Sep 142015 Sep 18

Other

Other41st European Solid-State Circuits Conference, ESSCIRC 2015
CountryAustria
CityGraz
Period15/9/1415/9/18

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Keywords

  • amplifier-sharing
  • delta-sigma modulator
  • I/Q mismatch
  • image-rejection

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yonekura, M., & Ishikuro, H. (2015). I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique. In European Solid-State Circuits Conference (Vol. 2015-October, pp. 229-232). [7313869] IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2015.7313869