Iterative procedure for designing the GenLOT

Takayuki Nagai; Shintaro Tsutsui; Masaaki Ikehara

Iterative procedure for designing the GenLOT

Takayuki Nagai, Shintaro Tsutsui, Masaaki Ikehara

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method require only to solve linear equations iteratively. Moreover, this algorithm converges within a few iteration.

Original language	English
Pages (from-to)	2689-2692
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
Publication status	Published - 1997 Jan 1
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 1997 Jun 9 → 1997 Jun 12

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{186f685a38fa449a8f8281038d3492f8,

title = "Iterative procedure for designing the GenLOT",

abstract = "In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method require only to solve linear equations iteratively. Moreover, this algorithm converges within a few iteration.",

author = "Takayuki Nagai and Shintaro Tsutsui and Masaaki Ikehara",

year = "1997",

month = jan,

day = "1",

language = "English",

volume = "4",

pages = "2689--2692",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

}

TY - JOUR

T1 - Iterative procedure for designing the GenLOT

AU - Nagai, Takayuki

AU - Tsutsui, Shintaro

AU - Ikehara, Masaaki

PY - 1997/1/1

Y1 - 1997/1/1

N2 - In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method require only to solve linear equations iteratively. Moreover, this algorithm converges within a few iteration.

AB - In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method require only to solve linear equations iteratively. Moreover, this algorithm converges within a few iteration.

UR - http://www.scopus.com/inward/record.url?scp=0030661040&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030661040&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030661040

VL - 4

SP - 2689

EP - 2692

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Iterative procedure for designing the GenLOT

Abstract

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this