TY - GEN
T1 - LaKe
T2 - 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018
AU - Tokusashi, Yuta
AU - Matsutani, Hiroki
AU - Zilberman, Noa
N1 - Funding Information:
1The version supported by the NetFPGA project. 2Note that the NetFPGA Reference Switch uses 13.91% of the Block RAM (BRAM) and 17.9% slice utilization
Funding Information:
ACKNOWLEDGMENT This work was supported by JSPS Research Fellowship and Keio University Research Grant for Young Researcher’s Program. This work was supported by JST CREST Grant Number JPMJCR1785, Japan. We acknowledge the support of the Leverhulme Trust (ECF-2016-289) and the Isaac Newton Trust.
PY - 2019/2/13
Y1 - 2019/2/13
N2 - In-network computing accelerates applications natively running on the host by executing them within network devices. While in-network computing offers significant performance improvements, its limitations and design trade-offs have not been explored. To usefully and efficiently run applications within the network, we first need to understand the implications of their design. In this work we introduce LaKe, a Layered Key-Value Store design, running as an in-network application. LaKe is a scalable design, enabling the exploration of design decisions and their effect on throughput, latency and power efficiency. LaKe achieves full line rate throughput, while maintaining a latency of 1.1 μs and better power efficiency than existing hardware based memcached designs.
AB - In-network computing accelerates applications natively running on the host by executing them within network devices. While in-network computing offers significant performance improvements, its limitations and design trade-offs have not been explored. To usefully and efficiently run applications within the network, we first need to understand the implications of their design. In this work we introduce LaKe, a Layered Key-Value Store design, running as an in-network application. LaKe is a scalable design, enabling the exploration of design decisions and their effect on throughput, latency and power efficiency. LaKe achieves full line rate throughput, while maintaining a latency of 1.1 μs and better power efficiency than existing hardware based memcached designs.
KW - Energy Efficiency
KW - FPGA
KW - In-network computing
KW - Key-value store
UR - http://www.scopus.com/inward/record.url?scp=85063158727&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85063158727&partnerID=8YFLogxK
U2 - 10.1109/RECONFIG.2018.8641696
DO - 10.1109/RECONFIG.2018.8641696
M3 - Conference contribution
AN - SCOPUS:85063158727
T3 - 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018
BT - 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018
A2 - Andrews, David
A2 - Feregrino, Claudia
A2 - Cumplido, Rene
A2 - Stroobandt, Dirk
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 3 December 2018 through 5 December 2018
ER -