Layout-conscious random topologies for HPC off-chip interconnects

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.

Original languageEnglish
Title of host publication19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
Pages484-495
Number of pages12
DOIs
Publication statusPublished - 2013 Jul 23
Event19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 - Shenzhen, China
Duration: 2013 Feb 232013 Feb 27

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
CountryChina
CityShenzhen
Period13/2/2313/2/27

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Keywords

  • Cabinet layout
  • High-performance computing
  • Interconnection networks
  • Network topologies

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Koibuchi, M., Fujiwara, I., Matsutani, H., & Casanova, H. (2013). Layout-conscious random topologies for HPC off-chip interconnects. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 (pp. 484-495). [6522343] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2013.6522343