Layout-conscious random topologies for HPC off-chip interconnects

Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.

Original languageEnglish
Title of host publicationProceedings - International Symposium on High-Performance Computer Architecture
Pages484-495
Number of pages12
DOIs
Publication statusPublished - 2013
Event19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013 - Shenzhen, China
Duration: 2013 Feb 232013 Feb 27

Other

Other19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013
CountryChina
CityShenzhen
Period13/2/2313/2/27

Fingerprint

Topology
Cables
Packaging
Communication
Constrained optimization

Keywords

  • Cabinet layout
  • High-performance computing
  • Interconnection networks
  • Network topologies

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Koibuchi, M., Fujiwara, I., Matsutani, H., & Casanova, H. (2013). Layout-conscious random topologies for HPC off-chip interconnects. In Proceedings - International Symposium on High-Performance Computer Architecture (pp. 484-495). [6522343] https://doi.org/10.1109/HPCA.2013.6522343

Layout-conscious random topologies for HPC off-chip interconnects. / Koibuchi, Michihiro; Fujiwara, Ikki; Matsutani, Hiroki; Casanova, Henri.

Proceedings - International Symposium on High-Performance Computer Architecture. 2013. p. 484-495 6522343.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Koibuchi, M, Fujiwara, I, Matsutani, H & Casanova, H 2013, Layout-conscious random topologies for HPC off-chip interconnects. in Proceedings - International Symposium on High-Performance Computer Architecture., 6522343, pp. 484-495, 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, 13/2/23. https://doi.org/10.1109/HPCA.2013.6522343
Koibuchi M, Fujiwara I, Matsutani H, Casanova H. Layout-conscious random topologies for HPC off-chip interconnects. In Proceedings - International Symposium on High-Performance Computer Architecture. 2013. p. 484-495. 6522343 https://doi.org/10.1109/HPCA.2013.6522343
Koibuchi, Michihiro ; Fujiwara, Ikki ; Matsutani, Hiroki ; Casanova, Henri. / Layout-conscious random topologies for HPC off-chip interconnects. Proceedings - International Symposium on High-Performance Computer Architecture. 2013. pp. 484-495
@inproceedings{28f5f2d9b133426a93466a7d1d2ac238,
title = "Layout-conscious random topologies for HPC off-chip interconnects",
abstract = "As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.",
keywords = "Cabinet layout, High-performance computing, Interconnection networks, Network topologies",
author = "Michihiro Koibuchi and Ikki Fujiwara and Hiroki Matsutani and Henri Casanova",
year = "2013",
doi = "10.1109/HPCA.2013.6522343",
language = "English",
isbn = "9781467355858",
pages = "484--495",
booktitle = "Proceedings - International Symposium on High-Performance Computer Architecture",

}

TY - GEN

T1 - Layout-conscious random topologies for HPC off-chip interconnects

AU - Koibuchi, Michihiro

AU - Fujiwara, Ikki

AU - Matsutani, Hiroki

AU - Casanova, Henri

PY - 2013

Y1 - 2013

N2 - As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.

AB - As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network topologies can be used to achieve low hop counts between nodes and thus low latency. However, random topologies lead to increased aggregate cable length and cable packaging complexity on a machine room floor. In this work we propose two new methods for generating random topologies and their physical layout on a floorplan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length. We quantitatively compare these two methods using both graph analysis and cycle-accurate network simulation, including comparisons with previously proposed random topologies and non-random topologies.

KW - Cabinet layout

KW - High-performance computing

KW - Interconnection networks

KW - Network topologies

UR - http://www.scopus.com/inward/record.url?scp=84880277841&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84880277841&partnerID=8YFLogxK

U2 - 10.1109/HPCA.2013.6522343

DO - 10.1109/HPCA.2013.6522343

M3 - Conference contribution

AN - SCOPUS:84880277841

SN - 9781467355858

SP - 484

EP - 495

BT - Proceedings - International Symposium on High-Performance Computer Architecture

ER -