Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using dual Vt cells

Kei'ichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

One of benefit of coarse-grained dynamically reconfigurable processor arrays (DRPAs) is their low dynamic power consumption by operating a number of processing element (PE) in parallel with a low frequency clock. However, in the future advanced process, the leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power of DRPA without severe performance degradation, eight designs (Mult, Sw, MultSw, LowHalf, 1Row, ColHalf, Sw+Half and Sw+Mult) using Dual-Vt cells are evaluated based on a prototype DRPA called MuCCRA-3T. Evaluation results show that Sw in which Low-Vt cells are only used in switching elements of the array achieved the best power-delay product. If performance of Sw is not enough, Sw+Half in which Low-Vt cells are used for a lower half PEs and all switching elements improves 24% of the leakage power with 5%-14% of extra delay time of the design with all Low-Vt cells.

Original languageEnglish
Title of host publicationProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages104-111
Number of pages8
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
Duration: 2009 Dec 92009 Dec 11

Publication series

NameProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
CountryAustralia
CitySydney
Period09/12/909/12/11

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software

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