Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Kimiyoshi Usami; Shunsuke Kogure; Yusuke Yoshida; Ryo Magasaki; Hideharu Amano

doi:10.1109/S3S.2017.8309226

Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET

Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.

Original language	English
Title of host publication	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538637654
DOIs	https://doi.org/10.1109/S3S.2017.8309226
Publication status	Published - 2018 Mar 7
Event	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States Duration: 2017 Oct 16 → 2017 Oct 18

Publication series

Name	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume	2018-March

Other

Other	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/Territory	United States
City	Burlingame
Period	17/10/16 → 17/10/18

Keywords

SOTB
body bias control
level shifter
multi-VDD

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/S3S.2017.8309226

Cite this

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R., & Amano, H. (2018). Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (pp. 1-3). (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2017.8309226

Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET. / Usami, Kimiyoshi; Kogure, Shunsuke; Yoshida, Yusuke; Magasaki, Ryo; Amano, Hideharu.

2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, K, Kogure, S, Yoshida, Y, Magasaki, R & Amano, H 2018, Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 17/10/16. https://doi.org/10.1109/S3S.2017.8309226

Usami K, Kogure S, Yoshida Y, Magasaki R, Amano H. Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-3. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017). https://doi.org/10.1109/S3S.2017.8309226

Usami, Kimiyoshi ; Kogure, Shunsuke ; Yoshida, Yusuke ; Magasaki, Ryo ; Amano, Hideharu. / Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017).

@inproceedings{77efcecab28b44939fbdd8c49da2b8c7,

title = "Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET",

abstract = "This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.",

keywords = "SOTB, body bias control, level shifter, multi-VDD",

author = "Kimiyoshi Usami and Shunsuke Kogure and Yusuke Yoshida and Ryo Magasaki and Hideharu Amano",

note = "Funding Information: ACKNOWLEDGMENT This work was partially supported by JSPS KAKENHI S Grant Number 25220002. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",

year = "2018",

month = mar,

day = "7",

doi = "10.1109/S3S.2017.8309226",

language = "English",

series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

}

TY - GEN

T1 - Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

AU - Usami, Kimiyoshi

AU - Kogure, Shunsuke

AU - Yoshida, Yusuke

AU - Magasaki, Ryo

AU - Amano, Hideharu

N1 - Funding Information: ACKNOWLEDGMENT This work was partially supported by JSPS KAKENHI S Grant Number 25220002. This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc. Publisher Copyright: © 2017 IEEE.

PY - 2018/3/7

Y1 - 2018/3/7

N2 - This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.

AB - This paper proposes a level-shifter free (LSF) approach for multi-VDD design to employ a combination of body bias control and a superior threshold-voltage (Vt) modulation capability of SOTB (Silicon on Thin BOX) devices. We applied this approach to a microprocessor test chip with low-voltage (VDDL) and high-voltage (VDDH) domains, and fabricated it in a 65nm SOTB technology. Measurement results demonstrated that the chip correctly operates at VDDL=0.6V and VDDH=1.2V under the reverse-body-bias (RBB) of 2V for pMOS transistors in the VDDH domain while suppressing the static dc current.

KW - SOTB

KW - body bias control

KW - level shifter

KW - multi-VDD

UR - http://www.scopus.com/inward/record.url?scp=85047645795&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85047645795&partnerID=8YFLogxK

U2 - 10.1109/S3S.2017.8309226

DO - 10.1109/S3S.2017.8309226

M3 - Conference contribution

AN - SCOPUS:85047645795

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 3

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -