Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.

Original languageEnglish
Title of host publication25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
PublisherIEEE Computer Society
ISBN (Electronic)9781538628805
DOIs
Publication statusPublished - 2017 Dec 13
Event25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates
Duration: 2017 Oct 23 → 2017 Oct 25

Other

Other25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
CountryUnited Arab Emirates
CityAbu Dhabi
Period17/10/23 → 17/10/25

Fingerprint

Electric potential
Threshold voltage
Transistors
Modulation
Costs

Keywords

  • Body bias control
  • FD-SOI
  • Level shifter
  • Low power
  • Multi-VDD design

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R., & Amano, H. (2017). Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings [8203473] IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203473

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. / Usami, Kimiyoshi; Kogure, Shunsuke; Yoshida, Yusuke; Magasaki, Ryo; Amano, Hideharu.

25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203473.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, K, Kogure, S, Yoshida, Y, Magasaki, R & Amano, H 2017, Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. in 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203473, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, 17/10/23. https://doi.org/10.1109/VLSI-SoC.2017.8203473
Usami K, Kogure S, Yoshida Y, Magasaki R, Amano H. Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society. 2017. 8203473 https://doi.org/10.1109/VLSI-SoC.2017.8203473
Usami, Kimiyoshi ; Kogure, Shunsuke ; Yoshida, Yusuke ; Magasaki, Ryo ; Amano, Hideharu. / Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017.
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abstract = "Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.",
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