Abstract
Level shifters to convert signal swings from low-voltage (VDDL) to high-voltage (VDDH) are required at the boundary of voltage domains in SoC employing multiple supply voltages. However, they cost delay, power and area in addition to increasing the complexity of physical design. This paper proposes a level-shifter-less (LSL) approach to use a reverse body bias (RBB) in the VDDH domain and superior threshold-voltage modulation capability of FD-SOI devices. Simulation results and measurements of a fabricated chip demonstrated that the chip applying the LSL approach correctly operates at VDDL=0.6V and VDDH=1.2V under RBB of 2V for pMOS transistors while suppressing the static dc current in the VDDH domain.
Original language | English |
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Title of host publication | 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings |
Publisher | IEEE Computer Society |
ISBN (Electronic) | 9781538628805 |
DOIs | |
Publication status | Published - 2017 Dec 13 |
Event | 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates Duration: 2017 Oct 23 → 2017 Oct 25 |
Other
Other | 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 |
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Country | United Arab Emirates |
City | Abu Dhabi |
Period | 17/10/23 → 17/10/25 |
Keywords
- Body bias control
- FD-SOI
- Level shifter
- Low power
- Multi-VDD design
ASJC Scopus subject areas
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering