LOREN

A scalable routing method for layout-conscious random topologies

Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. The trade-off is a large amount of routing information. For irregular networks, minimal routing is achieved by using routing tables for all destinations in the network. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 2.8% and improves the network throughput by up to 39% compared with a conventional compact routing method. Moreover, the required routing table size is reduced by up to 67%, which improves scalability and flexibility for implementation.

Original languageEnglish
Title of host publicationProceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages9-18
Number of pages10
ISBN (Electronic)9781509026555
DOIs
Publication statusPublished - 2017 Jan 13
Event4th International Symposium on Computing and Networking, CANDAR 2016 - Hiroshima, Japan
Duration: 2016 Nov 222016 Nov 25

Other

Other4th International Symposium on Computing and Networking, CANDAR 2016
CountryJapan
CityHiroshima
Period16/11/2216/11/25

Fingerprint

Network routing
Scalability
Switches
Throughput
Topology

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Signal Processing
  • Computer Networks and Communications

Cite this

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M., & Amano, H. (2017). LOREN: A scalable routing method for layout-conscious random topologies. In Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016 (pp. 9-18). [7818589] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CANDAR.2016.12

LOREN : A scalable routing method for layout-conscious random topologies. / Kawano, Ryuta; Nakahara, Hiroshi; Fujiwara, Ikki; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 9-18 7818589.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kawano, R, Nakahara, H, Fujiwara, I, Matsutani, H, Koibuchi, M & Amano, H 2017, LOREN: A scalable routing method for layout-conscious random topologies. in Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016., 7818589, Institute of Electrical and Electronics Engineers Inc., pp. 9-18, 4th International Symposium on Computing and Networking, CANDAR 2016, Hiroshima, Japan, 16/11/22. https://doi.org/10.1109/CANDAR.2016.12
Kawano R, Nakahara H, Fujiwara I, Matsutani H, Koibuchi M, Amano H. LOREN: A scalable routing method for layout-conscious random topologies. In Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 9-18. 7818589 https://doi.org/10.1109/CANDAR.2016.12
Kawano, Ryuta ; Nakahara, Hiroshi ; Fujiwara, Ikki ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / LOREN : A scalable routing method for layout-conscious random topologies. Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 9-18
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