Low power CMOS design challenges

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

Original languageEnglish
Pages (from-to)1021-1028
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE84-C
Issue number8
Publication statusPublished - 2001 Aug

Fingerprint

Energy dissipation
Communication

Keywords

  • Downsizing
  • Low power CMOS design
  • Low voltage
  • Subthreshold leakage current
  • Threshold voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Low power CMOS design challenges. / Kuroda, Tadahiro.

In: IEICE Transactions on Electronics, Vol. E84-C, No. 8, 08.2001, p. 1021-1028.

Research output: Contribution to journalArticle

@article{4815326eb51a4ebbb44ed16bbf68eb3a,
title = "Low power CMOS design challenges",
abstract = "Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.",
keywords = "Downsizing, Low power CMOS design, Low voltage, Subthreshold leakage current, Threshold voltage",
author = "Tadahiro Kuroda",
year = "2001",
month = "8",
language = "English",
volume = "E84-C",
pages = "1021--1028",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "8",

}

TY - JOUR

T1 - Low power CMOS design challenges

AU - Kuroda, Tadahiro

PY - 2001/8

Y1 - 2001/8

N2 - Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

AB - Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

KW - Downsizing

KW - Low power CMOS design

KW - Low voltage

KW - Subthreshold leakage current

KW - Threshold voltage

UR - http://www.scopus.com/inward/record.url?scp=0035421286&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035421286&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0035421286

VL - E84-C

SP - 1021

EP - 1028

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 8

ER -