Low-Power CMOS Digital Design with Dual Embedded Adaptive Power Supplies

Tadahiro Kuroda, Mototsugu Hamada

Research output: Contribution to journalArticle

47 Citations (Scopus)

Abstract

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.

Original languageEnglish
Pages (from-to)652-655
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume35
Issue number4
DOIs
Publication statusPublished - 2000 Apr 1
Externally publishedYes

Keywords

  • Adaptive power-supply system
  • Clustered voltage scaling
  • Low-power CMOS design
  • Multiple supply voltages

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Low-Power CMOS Digital Design with Dual Embedded Adaptive Power Supplies'. Together they form a unique fingerprint.

  • Cite this