Abstract
A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design.
| Original language | English |
|---|---|
| Pages (from-to) | 652-655 |
| Number of pages | 4 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 35 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2000 Apr |
| Externally published | Yes |
Keywords
- Adaptive power-supply system
- Clustered voltage scaling
- Low-power CMOS design
- Multiple supply voltages
ASJC Scopus subject areas
- Electrical and Electronic Engineering
