Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A kind of image processing with a low power Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3 implemented with 65nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3. The application design environment of MuCCRA-3 is also shown.

Original languageEnglish
Title of host publicationProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages364-367
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia
Duration: 2009 Dec 92009 Dec 11

Publication series

NameProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other2009 International Conference on Field-Programmable Technology, FPT'09
CountryAustralia
CitySydney
Period09/12/909/12/11

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software

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  • Cite this

    Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., & Amano, H. (2009). Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09 (pp. 364-367). [5377614] (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09). https://doi.org/10.1109/FPT.2009.5377614