Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano

doi:10.1109/FPT.2009.5377614

Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A kind of image processing with a low power Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3 implemented with 65nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3. The application design environment of MuCCRA-3 is also shown.

Original language	English
Title of host publication	Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09
Pages	364-367
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2009.5377614
Publication status	Published - 2009 Dec 1
Event	2009 International Conference on Field-Programmable Technology, FPT'09 - Sydney, Australia Duration: 2009 Dec 9 → 2009 Dec 11

Publication series

Name	Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Other

Other	2009 International Conference on Field-Programmable Technology, FPT'09
Country/Territory	Australia
City	Sydney
Period	09/12/9 → 09/12/11

ASJC Scopus subject areas

Computational Theory and Mathematics
Hardware and Architecture
Software

Access to Document

10.1109/FPT.2009.5377614

Cite this

Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., & Amano, H. (2009). Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09 (pp. 364-367). [5377614] (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09). https://doi.org/10.1109/FPT.2009.5377614

Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array. / Kimura, Masayuki; Saito, Yoshiki; Sano, Toru et al.
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. 2009. p. 364-367 5377614 (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kimura, M, Saito, Y, Sano, T, Kato, M, Tunbunheng, V, Yasuda, Y & Amano, H 2009, Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array. in Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09., 5377614, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, pp. 364-367, 2009 International Conference on Field-Programmable Technology, FPT'09, Sydney, Australia, 09/12/9. https://doi.org/10.1109/FPT.2009.5377614

Kimura M, Saito Y, Sano T, Kato M, Tunbunheng V, Yasuda Y et al. Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. 2009. p. 364-367. 5377614. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09). doi: 10.1109/FPT.2009.5377614

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abstract = "A kind of image processing with a low power Dynamically Reconfigurable Processor Array (DRPA) prototype MuCCRA-3 implemented with 65nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3. The application design environment of MuCCRA-3 is also shown.",

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Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

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