Low-power network-packet-processing architecture using process-learning cache for high-end backbone router

Michitaka Okuno, Shin Ichi Ishida, Hiroaki Nishi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i.e., table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-μm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

Original languageEnglish
Pages (from-to)536-543
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE88-C
Issue number4
DOIs
Publication statusPublished - 2005 Apr

Fingerprint

Packet networks
Routers
Processing
Throughput
Gears
Engines
Electric power utilization
Silicon

Keywords

  • Cache-based packet-processing engine
  • Ethernet
  • Network processor
  • Packet-processing engine
  • Router

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Low-power network-packet-processing architecture using process-learning cache for high-end backbone router. / Okuno, Michitaka; Ishida, Shin Ichi; Nishi, Hiroaki.

In: IEICE Transactions on Electronics, Vol. E88-C, No. 4, 04.2005, p. 536-543.

Research output: Contribution to journalArticle

@article{c211254f4a4d4a3f8a294ea7324c1ca9,
title = "Low-power network-packet-processing architecture using process-learning cache for high-end backbone router",
abstract = "A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i.e., table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-μm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5{\%} of the die size and 32.8{\%} of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.",
keywords = "Cache-based packet-processing engine, Ethernet, Network processor, Packet-processing engine, Router",
author = "Michitaka Okuno and Ishida, {Shin Ichi} and Hiroaki Nishi",
year = "2005",
month = "4",
doi = "10.1093/ietele/e88-c.4.536",
language = "English",
volume = "E88-C",
pages = "536--543",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "4",

}

TY - JOUR

T1 - Low-power network-packet-processing architecture using process-learning cache for high-end backbone router

AU - Okuno, Michitaka

AU - Ishida, Shin Ichi

AU - Nishi, Hiroaki

PY - 2005/4

Y1 - 2005/4

N2 - A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i.e., table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-μm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

AB - A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i.e., table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-μm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

KW - Cache-based packet-processing engine

KW - Ethernet

KW - Network processor

KW - Packet-processing engine

KW - Router

UR - http://www.scopus.com/inward/record.url?scp=33645579965&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33645579965&partnerID=8YFLogxK

U2 - 10.1093/ietele/e88-c.4.536

DO - 10.1093/ietele/e88-c.4.536

M3 - Article

AN - SCOPUS:33645579965

VL - E88-C

SP - 536

EP - 543

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 4

ER -