Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI

Satoshi Gounai, Tomoaki Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves Maximum Likelihood (ML) decoding. The ML decoding is effective to lower error floors. However, temporal estimates obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. The OSD algorithm can not lower error floors due to the temporal estimates satisfying the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Due to CRC we can detect errors from the codeword estimated by the OSD algorithm. Our proposed LDPC code with the proposed decoding can lower error floors in an AWGN channel. However, in wireless access environments, we can not neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit In this paper, we evaluate the BLock Error Rate (BLER) of the proposed LDPC code with the proposed decoding in a fast fading channel with and without perfect CSI where 'without perfect CSI' means that only the average of the fading amplitudes is known at the receiver. From the computer simulation, we show that the proposed LDPC code with the proposed decoding can lower error floors than the conventional LDPC code with the OSD algorithm in the fast fading channel with and without perfect CSI.

Original languageEnglish
Title of host publicationIEEE Vehicular Technology Conference
Pages634-638
Number of pages5
Volume61
Edition1
Publication statusPublished - 2005
Externally publishedYes
Event2005 IEEE 61st Vehicular Technology Conference -VTC 2005 - Spring Stockholm: Paving the Path for a Wireless Future - Stockholm, Sweden
Duration: 2005 May 302005 Jun 1

Other

Other2005 IEEE 61st Vehicular Technology Conference -VTC 2005 - Spring Stockholm: Paving the Path for a Wireless Future
CountrySweden
CityStockholm
Period05/5/3005/6/1

Fingerprint

Channel state information
Decoding
Statistics
Fading channels
Maximum likelihood
Redundancy
Concatenated codes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Gounai, S., & Ohtsuki, T. (2005). Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI. In IEEE Vehicular Technology Conference (1 ed., Vol. 61, pp. 634-638)

Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI. / Gounai, Satoshi; Ohtsuki, Tomoaki.

IEEE Vehicular Technology Conference. Vol. 61 1. ed. 2005. p. 634-638.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gounai, S & Ohtsuki, T 2005, Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI. in IEEE Vehicular Technology Conference. 1 edn, vol. 61, pp. 634-638, 2005 IEEE 61st Vehicular Technology Conference -VTC 2005 - Spring Stockholm: Paving the Path for a Wireless Future, Stockholm, Sweden, 05/5/30.
Gounai S, Ohtsuki T. Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI. In IEEE Vehicular Technology Conference. 1 ed. Vol. 61. 2005. p. 634-638
Gounai, Satoshi ; Ohtsuki, Tomoaki. / Lowering error floors of irregular LDPC code on fast fading environment with and without perfect CSI. IEEE Vehicular Technology Conference. Vol. 61 1. ed. 2005. pp. 634-638
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