MAPLE chip: A processing element for a static scheduling centric multiprocessor

K. Yasufuku, R. Ogawa, K. Iwai, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A custom processor called MAPLE, which supports static scheduling by automatic parallelizing compilers, is implemented and evaluated. MAPLE has a high performance floating point arithmetic unit and low latency data transfer mechanism for other MAPLE chips. The maximum operational frequency is 80 MHz in simulation, and the operation on the prototype board with 23 MHz clock is confirmed. It requires about 0.56 W at 23 MHz operation.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages575-576
Number of pages2
Volume2003-January
ISBN (Print)0780376595
DOIs
Publication statusPublished - 2003
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03/1/2103/1/24

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Yasufuku, K., Ogawa, R., Iwai, K., & Amano, H. (2003). MAPLE chip: A processing element for a static scheduling centric multiprocessor. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2003-January, pp. 575-576). [1195085] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195085