MINC: Multistage interconnection network with cache control mechanism

Toshihiro Hanawa, Takayuki Kamei, Hideki Yasukawa, Katsunobu Nishimura, Hideharu Amano, Nobuo Tsudat

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the shared memory using the Reduced Hierarchical Bit-map Directory schemes (RHBDs). In the RHBD, the bit-map directory is reduced and carried in the packet header for quick multicasting without accessing the directory in each hierarchy. In order to reduce unnecessary packets caused by compacting the bit map in the RHBD, a small cache called the pruning cache is introduced in the switching element. The simulation reveals the pruning cache works most effectively when it is provided in every switching element of the first stage, and it reduces the congestion more than 50% with only 4 entries. The MINC cache control chip with 16 inputs/outputs is implemented on the LPGA (Laser Programmable Gate Array), and works with a 66 MHz clock. Fault-Tolerant Cube-Connected Cycles Architectures Capable of Quick Broadcasting by Using Spare Circuits. The construction of fault-tolerant processor arrays with interconnections of cube-connected cycles (CCCs) by using an advanced spare-connection scheme for fc-out-of-n redundancies called "generalized additional bypass linking" is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The spare connections are designed as a node-coloring problem of a CCC graph with a minimum distance of 3: the chromatic numbers corresponding to the number of spare PE connections were evaluated theoretically. The proposed scheme can be used for constructing various fc-outof-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control. In particular, it allows construction of optimal r-fault-tolerant configurations that provide r spare PEs and r extra connections per PE for CCCs with Ax PEs (x : integer) in each cycle.

Original languageEnglish
Pages (from-to)863-870
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE80-D
Issue number9
Publication statusPublished - 1997 Jan 1

Keywords

  • Additional bypass linking
  • Coherent cache
  • Congestion analysis
  • Cube-connected cycles
  • Directory scheme
  • Fault-tolerant
  • MIN
  • Multiprocessor
  • Node coloring
  • Quick broadcasting
  • Vlsi implementation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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  • Cite this

    Hanawa, T., Kamei, T., Yasukawa, H., Nishimura, K., Amano, H., & Tsudat, N. (1997). MINC: Multistage interconnection network with cache control mechanism. IEICE Transactions on Information and Systems, E80-D(9), 863-870.