MINC (Multistage Interconnection Network with Cache control mechanism) chip

Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

In a Multistage Interconnection Networks (MINs), a snoop cache technique in bus connected multiprocessors cannot be used, and consistency problems must be solved for providing the cache memory between a processor and the switch. To solve these problems, the MINC (MIN with Cache control mechanism) is proposed. In the MINC, cache coherent messages is separated from the data transfer network, and pushed into an LSI chip called the MINC chip. The coherent control is done based on the directory using the Reduced Hierarchical Bit-map Directory scheme (RHBD).

Original languageEnglish
Pages337-338
Number of pages2
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
Duration: 1998 Feb 101998 Feb 13

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period98/2/1098/2/13

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Midorikawa, T., Kamei, T., Hanawa, T., & Amano, H. (1998). MINC (Multistage Interconnection Network with Cache control mechanism) chip. 337-338. Paper presented at Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, .