Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Contribution to journalArticle

    11 Citations (Scopus)

    Abstract

    Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

    Original languageEnglish
    Article number5208378
    Pages (from-to)1238-1243
    Number of pages6
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Volume18
    Issue number8
    DOIs
    Publication statusPublished - 2010 Aug 1

    Keywords

    • High-speed interconnect
    • SiP
    • low-power design
    • misalignment
    • wireless interconnect

    ASJC Scopus subject areas

    • Software
    • Hardware and Architecture
    • Electrical and Electronic Engineering

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