Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

Original languageEnglish
Article number5208378
Pages (from-to)1238-1243
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number8
DOIs
Publication statusPublished - 2010 Aug

Fingerprint

Transmitters
Communication

Keywords

  • High-speed interconnect
  • low-power design
  • misalignment
  • SiP
  • wireless interconnect

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration. / Niitsu, Kiichi; Kohama, Yoshinori; Sugimori, Yasufumi; Kasuga, Kazutaka; Osada, Kenichi; Irie, Naohiko; Ishikuro, Hiroki; Kuroda, Tadahiro.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 8, 5208378, 08.2010, p. 1238-1243.

Research output: Contribution to journalArticle

@article{bf4db0b369cf4d25bf1818fb4396499e,
title = "Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration",
abstract = "Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.",
keywords = "High-speed interconnect, low-power design, misalignment, SiP, wireless interconnect",
author = "Kiichi Niitsu and Yoshinori Kohama and Yasufumi Sugimori and Kazutaka Kasuga and Kenichi Osada and Naohiko Irie and Hiroki Ishikuro and Tadahiro Kuroda",
year = "2010",
month = "8",
doi = "10.1109/TVLSI.2009.2020724",
language = "English",
volume = "18",
pages = "1238--1243",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration

AU - Niitsu, Kiichi

AU - Kohama, Yoshinori

AU - Sugimori, Yasufumi

AU - Kasuga, Kazutaka

AU - Osada, Kenichi

AU - Irie, Naohiko

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

PY - 2010/8

Y1 - 2010/8

N2 - Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

AB - Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.

KW - High-speed interconnect

KW - low-power design

KW - misalignment

KW - SiP

KW - wireless interconnect

UR - http://www.scopus.com/inward/record.url?scp=77955174093&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955174093&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2009.2020724

DO - 10.1109/TVLSI.2009.2020724

M3 - Article

VL - 18

SP - 1238

EP - 1243

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 8

M1 - 5208378

ER -