MS synchronization networks using digital signal processing PLL with different phase error averaging number in each slave level

Minobu Hayashi, Zaihua Luan, Iwao Sasase, Shinsaku Mori

Research output: Contribution to journalArticlepeer-review

Abstract

When the scale of a network is expanded in the master‐slave synchronization system, a problem occurs in that the jitter produced in the upper‐level station propagates and accumulates in the lower‐level station. This paper proposes a master‐slave synchronization network, where the digital signal processing PLL averaging different phase errors is used at each level, with the number of averaging depending on the level. The network in which the number of averaging increases linearly from the upper to the lower level, as well as the network in which the number of averaging increases nonlinearly according to the accumulation of the jitter are considered. It is shown that the jitter characteristic for the whole network is improved for the same acquisition time compared to the network with the uniform number of averaging. With regard to the two networks considered, the optimal increment is derived for the linearly increasing case. It is shown that the improvement is more remarkable in the second network than in the first, and the improvement is more remarkable in either network with the increase of the network scale.

Original languageEnglish
Pages (from-to)12-20
Number of pages9
JournalElectronics and Communications in Japan (Part I: Communications)
Volume75
Issue number3
DOIs
Publication statusPublished - 1992

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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